參數(shù)資料
型號: NS32FX100VF
廠商: National Semiconductor Corporation
英文描述: System Controller
中文描述: 系統(tǒng)控制器
文件頁數(shù): 35/94頁
文件大?。?/td> 955K
代理商: NS32FX100VF
2.0 Architecture
(Continued)
TL/EE/11331–23
FIGURE 2-18. DMA I/O to Memory Write Transaction (DIR
e
1, NFBY
e
1)
The maximum throughput of a DMA channel is 3.125 Mbyte/sec. (One byte can be transferred at a rate of eight CTTL cycles per
transfer, up to 25 MHz.)
Note 1:
Memory control signals (like CWAIT, select and write enable) are generated according to the specifications of the accessed zone.
Note 2:
The NS32FX100 does not drive data onto AD0–15 till the end of T4 in memory
Y
I/O transactions (like NS32FX100 register read transactions).
Note 3:
A
v
in the figure indicates DMA priority resolving points.
35
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