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參數(shù)資料
| 型號(hào)： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 12/94頁 |
| 文件大?。?/td> | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
(Continued)
2.2.3 Registers
CSCL:
CCLK (CPU Input Clock) Scale register.
7
5
4
3
0
res
F
res
F:
Controls the CCLK frequency.
1: The CCLK frequency is the FOSCI input
frequency divided by 16.
0: The CCLK frequency is the FOSCI input
frequency.
Upon reset F is set to ‘‘1’’.
res: Reserved
MCLOFF: MCLK Off Time. 8-bit register.
MCLOFF should be set to a fixed value, as
shown in Table I, as a function of CTTL in nor-
mal operation mode, to generate a 1.2288 MHz
clock, thus controlling the CTTL duty cycle.
MCLON:
MCLK On Time. 8-bit register.
MCLON should be set to a fixed value, as
shown in Table I, as a function of CTTL in nor-
mal operation mode, to generate a 1.2288 MHz
clock, thus controlling the CTTL duty cycle.
TABLE 2-1. CTTL, MCLON and MCLOFF Values
CTTL (MHz)
MCLON
MCLOFF
14.7456
15.9744
17.2032
18.4320
19.6608
20.8896
22.1184
23.3472
24.5760
5
6
6
7
7
8
8
9
9
5
5
6
6
7
7
8
8
9
TIMER:
Programmable Timer.
15
0
TIMER
TIMER:
The actual counter bits.
TIMER is a programmable, retriggerable, down counter
which generates an interrupt pulse after a programmable
number of MCLK cycles. When it goes below zero it stops
counting and holds the value 0x0ffff. If a new value is written
to the TIMER before it reaches zero, it starts counting down
from this new value. Reading TIMER gives its current con-
tents.
Each bit in the TIMER register stands for 0.8
m
s (1/1.2288
MHz), thus the counter may represent the maximum value
of 0.8 x 2
16
m
s.
Writing ‘‘0’’ to the timer is not allowed.
BUZCFG: Buzzer Configuration register.
7
6
5
0
BCTRL
res
BCTRL:
Used to control the BUZCLK pin.
00 : BUZCLK pin
e
0.
01 : BUZCLK pin
e
1.
10 : BUZCLK pin
e
symmetric square wave,
according to BUZSWC register.
11 : Reserved.
BUZSWC: Buzzer Square Wave Counter. 16-bit register.
Used for dividing MCLK to generate a symmetric
square wave on the BUZCLK pin, as follows:
BUZCLK frequency
e
MCLK/(2
*
BUZSWC
a
2).
WATCHDOG Counter. 8-bit register.
WDC:
The WATCHDOG Counter (WDC) is a down
counter that counts STIC pulses. The counter
generates a trap signal, on the WATCHDOG
Trap (WDT) pin, if the counter reaches zero, or if
WDC is written into more than once per STIC
cycle. After reset WDC is idle (not counting). It
starts counting after it is first written, starting
from the value that is written into it. Once start-
ed, WDC can be stopped only by a hardware
reset.
The WATCHDOG counts STIC pulses which are
generated by the TCU. Therefore the WATCH-
DOG is functional only when the TCU’s counters
are enabled by the MCFG.ECOUNT bit.
Writing ‘‘0’’ to the timer is not allowed.
TSL:
Time Slot down counter. 8-bit, read only.
Holds the current time slot. Upon reset the TSL
bits are set to ‘‘1’’.
ETC:
Elapsed Time Counter. A 32-bit down counter
that counts at a rate of the slow clock (SOSCI)
divided by 512.
Accessed as double-word only.
Not affected by reset.
At least four slow-clock cycles are required, be-
tween a write and any accesses to ETC, to
avoid unpredictable results.
Successive reads from the ETC may differ from
each other by two.
Example:
Read ETC, value
e
n (correct value should be
n
a
1)
Read ETC, value
e
n
a
2 (correct value).
Refresh Rate Control. 8-bit register.
The refresh is set to occur once every (RFRT
a
1) cycles of the slow clock. RFRT must be set to
a minimum value of 3.
RFRT:
The actual refresh transaction may be post-
poned due to synchronization with the fast clock
and with other memory transactions.
12
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