參數(shù)資料
型號： NS32FX100VF
廠商： National Semiconductor Corporation
英文描述： System Controller
中文描述： 系統(tǒng)控制器
文件頁數(shù)： 63/94頁
文件大?。?/td> 955K
代理商： NS32FX100VF
4.0 Device Specifications
(Continued)
4.1.3 Output Signals
Signal
Pin Numbers
Description
BUZCLK
59
Buzzer ClockD
Programmable frequency clock for the buzzer.
CAS
104
DRAM Column Address StrobeD
Column address strobe for DRAM banks refresh.
(NS32FX200 and NS32FV100.)
CCLK
39
CPU Double ClockD
Feeds CPU’S OSCIN. Asynchronous
CWAIT
103
Continuous WaitD
Low extends the memory cycle of the CPU.
DMAK1
28
DMA AcknowledgeD
Output for DMA channel 1 acknowledge or general purpose
output pin.
DMAK3
26
DMA AcknowledgeD
Output for DMA channel 3 acknowledge or general purpose
output pin.
FOSCO
37
High-Speed Oscillator OutD
Asynchronous. This line is used as the return path for
the crystal (if used).
HOLD
115
Hold RequestD
When low, HOLD requests the bus from the CPU to perform DMA
operations or to insert idle bus cycles.
INTR
44
Interrupt RequestD
Low indicates that an interrupt request is being output to the CPU.
MA1–15
101
98
94
91
87
100
97
93
89
86
99
95
92
88
85
Memory Address BusD
Multiplexed DRAM address. (NS32FX200 and NS32FV100.)
MWSK
24
MICROWIRE Shift ClockD
Output or general purpose output pin.
OE
111
Output EnableD
Used by the addressed device to gate the data onto the data bus.
PDO
16
Printer Bitmap Shifter DataD
Output from the bitmap shifter.
PEXT
65
External Expansion Port Latch Enable.
PMPH0–3
74
71
73
72
Printer Motor PhasesD
Four phase signals for driving the printer motor.
RAS0
106
DRAM Row Address StrobesD
Row address strobe for DRAM banks 0 and 1.
(NS32FX200 and NS32FV100.)
RAS1
105
SCLK1
22
Scanner Clock 1D
Output, pixel clock or general purpose output pin.
SCLK2/DMAK0
29
Scanner Clock 2D
Output, pixel clock or DMA AcknowledgeDoutput for DMA channel
0 acknowledge or general purpose output pin.
SCVO
79
Scanner Compensated Video OutD
Analog current for use by ABC or optional video
enhancement circuit.
SDFDBK
18
Sigma-Delta FeedbackD
Feedback input to the SDC analog receiver. Asynchronous
output signal.
63
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