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參數(shù)資料
| 型號： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 38/94頁 |
| 文件大?。?/td> | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
(Continued)
7
6
5
4
3
2
1
0
TBRK
res
res
res
TSB
EDB
PEN
EPS
EPS:
Even Parity Select.
0 : Odd parity
1 : Even parity
Even parity means that the total number of bits
set (including the parity bit) is even.
PEN:
Parity Enable.
0 : Parity disabled
1 : Parity enabled
EDB:
Number of data bits.
0 : Seven data bits
1 : Eight data bits
TSB:
Number of stop bits transmitted.
0 : One stop bit
1 : Two stop bits
TBRK:
Transmission Break ControlDimplemented by
forcing UTXD pin low.
0 : No break signal
1 : Break signal
Undefined results when TBRK is ‘‘1’’ while
UCLST:
UART Clearing Status register. 8-bit register.
7
6
5
4
3
2
1
0
TR
TE
res
OE
res
FE
PE
RF
Receive status bits: Upon reset, these status bits are
cleared to ‘‘0’’.
RF: Receive Full. RF
e
1 when URXB is loaded by the
shift register.
PE: Parity Error. PE
e
1 when parity error is detected.
FE: Frame Error. FE
e
1 when the first stop bit is ‘‘0’’.
OE: Overrun Error. OE
e
1 when both reception buffer and
shifter are full and a new character is received.
Transmit status bits: Upon reset, these status bits are set to
‘‘1’’.
TE: Transmit Empty. TE
e
1 when both UTXB and the
shifter are empty.
TR: Transmit Ready. TR
e
1 when UTXB is empty.
OE status bit is sticky. Once set, it is cleared by reset or by
writing into UCLST (data written into this register is ignored).
RF is cleared during reset. It is set to ‘‘1’’ when URXB is
loaded by the shift register. It is updated by a URXB read:
RF remains ‘‘1’’ if the shifter already holds a new character,
and is cleared to ‘‘0’’ if the shifter did not finish reception of
a new character.
PE and FE bits are sticky. These two bits are cleared during
reset and whenever UCLST is read.
2.7.4 Usage Recommendations
1. Before activating the UART, program the appropriate
Ports module registers PADI, PAMS, PBDO, PBMS,
PCDO, PCMS and PCEN to connect the UART module
to the NS32FX100 I/O pins.
2. Initialization:
a. Disable interrupts or mask the UART interrupt.
b. Initialize UBRG and then UCNTL.
c. Clear receiver status bits using URXB and UCLST.
d. Enable UART interrupt, if required.
e. Program the PAMS register in the Ports module as
follows:
MS0 must be cleared before data is trans-
mitted from the UART.
MS1 must be set before data can be re-
ceived on the URXT pin.
3. To use the PE and FE status bits as non-sticky bits, read
the UCLST before reading URXB. Note that right after
URXB is read, it might be loaded with a new character
which was waiting in the shifter, and those status bits
might be set by the new URXB. Therefore, it is recom-
mended to read UCLST first and then read URXB, thus
keeping coherence between the contents of URXB and
UCLST.
4. When UTEN is inactive, the TE bit does not ensure that
two characters may be written to the UTXB. The TR bit
must be ‘‘0’’ before each UTXB write.
2.8 MICROWIRE (MWIRE)
2.8.1 Features
Y
Operates as a MICROWIRE master
Y
Programmable shift-clock frequency
Y
8-bit serial I/O data shift register
Y
Busy flag for polling and as an interrupt source
Y
Two modes of clocking data
2.8.2 Operation
The MICROWIRE (MWIRE) is a serial synchronous commu-
nication interface. It enables an interface with any National
Semiconductor chip that supports MICROWIRE protocol,
such as COPs and EEPROMs. The MWIRE interface con-
sists of three signals: serial data in, serial data out, and
serial clock. Several devices may share the same MWIRE
channel by means of device-select signals. Such select sig-
nals may be provided by the Ports module. The MWIRE
outputs may be TRI-STATED by the Ports module. A high
level interrupt is generated when the MWIRE is not busy,
and is cleared only while MWIRE is busy. The serial data is
sampled on the serial clock falling edge. The serial data out
may change on the serial clock rising or falling edge, ac-
cording to the software selected mode.
2.8.3 Registers
MWSIO:
MICROWIRE Serial I/O Shift register. 8-bit shift
register.
Used for data transfer over the MWIRE channel.
Bit-7, the most significant bit, is transmitted first.
38
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