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參數(shù)資料
| 型號： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 10/94頁 |
| 文件大?。?/td> | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
2.1 MCFGDMODULE CONFIGURATION REGISTER
The software can configure some of the NS32FX100 major
operation modes by programming the Module Configuration
Register (MCFG). Some of the bits in this register are also
used to initialize the TPH block in the PRNTC, the bitmap
shfiter block in the PRNTC and the scanner module. When
a bit in the MCFG is ‘‘0’’, the associated module is idle.
Setting a bit to ‘‘1’’ enables the operation of the associated
module. Prior to activating a module, its appropriate regis-
ters must be initialized by software.
15
6
5
4
3
2
1
0
res
ESDC
EDMA0
ESCAN
EPBMS
ETPHB
ECOUNT
ECOUNT: Enable internal counters of the TCU module.
Once set, this bit can not be cleared by software.
The TCU counters, except TIMER and WDC,
must be initialized prior to setting this bit since
they start working when the ECOUNT bit is set.
ETPHB:
Enable Thermal Print-Head Block of the PRNTC
module. The strobe-on and strobe-off counters
of this block must be initialized prior to setting
this bit to ‘‘1’’.
EPBMS:
Enable Bitmap Shifter Block of the PRNTC mod-
ule. Clearing this bit is treated, by the Bitmap
Shifter, as a hardware reset. The block starts op-
erating when this bit is set. When disabled, DMA
channel 1 uses the printer PCLK/DMRQ1 pin.
ESCAN:
Enable Scanner module. Clearing this bit is treat-
ed, by the Scanner Controller, as a hardware re-
set. The module starts operating when this bit is
set. When cleared to ‘‘0’’, DMA channel 2 uses
the scanner pins and interrupt.
EDMA0:
Enable scanner usage of DMA channel 0. When
cleared to ‘‘0’’, DMA channel 0 uses the scanner
pins and interrupt.
ESDC:
Enable Sigma-Delta CODEC module. When this
bit is set the SDC operation takes place as de-
scribed in Section 2.3.
Upon reset the non reserved bits of the MCFG are cleared
to ‘‘0’’, thus disabling the above modules and options.
2.2 TIMING CONTROL UNIT (TCU)
2.2.1 Features
#
Generation and control of clock running frequency
#
CPU and NS32FX100 synchronization by Phase Lock
Loop (PLL)
#
Fixed System-Tick interrupt of 100 Hz
#
WATCHDOG
#
Timer
#
Buzzer
#
Freeze mode
2.2.2 Operation
The Timing Control Unit (TCU) is responsible for generating
the clocks, used for the various timing and counting func-
tions in the system, and for freeze mode operation. Figure
2-1 shows how the clocks are connected in an NS32FX100-
based FAX system.
TL/EE/11331–6
FIGURE 2-1. Clocks and Traps Connectivity
10
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