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參數(shù)資料
| 型號： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 43/94頁 |
| 文件大?。?/td> | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
(Continued)
Four bits are associated with each general purpose I/O pin
of this port:
DI: Data In Bit
DO: Data Out Bit
EN: Enable Bit
MS: Module Select Bit
Port input data is asynchronous. When the input is read
while it is changing, the value read is unreliable. The soft-
ware should read an input either when it is guaranteed that
the input is stable, or perform debouncing. If the input satis-
fies the required set-up and hold times, the value read is the
true input value. With the exception of URXD and UTEN,
when an input is assigned to a module it must satisfy the
required set-up and hold times. The results are unpredict-
able if this requirement is not satisfied.
2.10.2.2 External Output Port Extension
The number of output ports of an NS32FX100-based FAX
system can be expanded by an external latch, such as the
DM74LS373 chip. Two such latches can add 16 output pins
without any additional glue logic. This module controls such
an external latch.
TL/EE/11331–31
FIGURE 2-26. External Output Port Extension
The latch data inputs are taken from the system data bus.
The latching signal is generated by the NS32FX100. The
NS32FX100 includes the PEXT register, which is an on-chip
mirror register of the external latch. This is used to ease the
setting, or clearing, of individual bits by enabling the CPU to
read back the port value, modify the required bit(s) and write
the new value to the external latch. The read back is per-
formed from PEXT rather than from the write-only external
latch. Writing is performed simultaneously to both the exter-
nal latch and to PEXT. The external latching signal is gener-
ated when PEXT is being written into. i.e., at T3 of the write
transaction. It is also active during reset to enable initializa-
tion of the external output port extension.
2.10.2.3 Stepper Motors Output Ports
The stepper motor is controlled by four phases. The phases
values are stored by software into the Ports module regis-
ters and are transferred into the phase pins by the motor
interrupt pulse rising edge.
2.10.3 Registers
PADI:
Port A data in. Read only.
Each bit holds the current value of the correspond-
ing input pin.
7
4
3
2
1
0
res
DMRQ3
MWSI
URXD
UTEN
PAMS:
Port A module select.
7
2
1
0
res
MS1
MS0
MS0, MS1: Module select bits for Port A input pins.
The UART’s UTEN input is forced low when
MS0
e
0.
The UART’s URXD input is forced high when
MS1
e
0.
Reserved
res:
MS0 must be cleared before data is transmitted from the
UART.
MS1 must be set before data can be received on the
URXD pin.
Upon reset this register is cleared to ‘‘0’’.
PBDO: Port B data out.
Each bit holds the value driven onto the corre-
sponding output pin when the respective MS bit, in
the PBMS register, is ‘‘0’’.
7
6
5
4
3
2
1
0
DMAK3
SDIS/
DMAK1
SCLK2/
STB3
STB2
STB1
STB0
DMAK2
DMAK0
15
12
11
10
9
8
res
SLS
SCLK1
SPDW
MSWK
PBMS: Port B module select.
15 12
11
10
9
8
7
6
5
4
3
2
1
0
res
MS11 MS10 MS9 MS8 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0
MS0–MS11: Module select bits for Port B output pins.
0 : Port is selected.
The value of the corresponding bit in the PBDO regis-
ter is driven on the respective pin, when Port B is en-
abled through the PBEM register.
1 : Module is selected.
The value of the pin specified by the corresponding bit
in the PBDO register is driven from the appropriate
module: Printer, Scanner, DMA.
Upon reset this register is cleared to ‘‘0’’.
When the Scanner or the DMA module is activated through
the MCFG register, MS4 and MS6 must be set to ‘‘1’’ as
detailed in the following table:
Module MCFG.EDMA0 MS4 Module MCFG.ESCAN MS6
DMA
0
1
DMA
0
1
Scanner
1
1
Scanner
1
1
Port
X
0
Port
X
0
PBEN:
Port B enable.
15
1
0
res
EN
EN:
Controls the pins’ state. All pins are driven when
this bit is set. Upon reset bit 0 is cleared, causing
the output pins to be in TRI-STATE.
43
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