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參數(shù)資料
| 型號： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 36/94頁 |
| 文件大?。?/td> | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
(Continued)
TL/EE/11331–24
FIGURE 2-19. Two Adjacent Fly-By DMA Transactions
The maximum throughput of a DMA channel is 12.5 Mbyte/sec. (Two bytes can be transferred at a rate of four CTTL cycles per
transfer, up to 25 MHz.)
Note 1:
Memory control signals (like CWAIT, select and write enable) are generated according to the specifications of the accessed zone.
Note 2:
A
v
in the figure indicates DMA priority resolving points.
2.7 UNIVERSAL ASYNCHRONOUS RECEIVER-
TRANSMITTER (UART)
2.7.1 Features
Y
Full duplex double-buffered transmitter/receiver
Y
Programmable baud rate between 300 and CTTL/32
baud
Y
Hardware flow control
Y
Asynchronous 7-bit or 8-bit character transmission/
reception
Y
Supports transmission of one or two stop bits
Y
Hardware support of odd or even parity-bit generation
during transmission
Y
Hardware support of odd or even parity check during
reception
Y
Maskable interrupt on transmit ready or receive ready,
regardless of reception errors
Y
Data sampled at 16 times the baud rate
Y
Software-controlled break transmission and detection
2.7.2 Operation
The Universal Asynchronous Receiver Transmitter (UART)
module enables the NS32FX100 to communicate with stan-
dard serial devices using three communication signals:
transmit, receive and ground. A character is composed of a
start bit followed by data bits (the least significant bit right
after the start bit) followed by an optional parity bit and at
least one stop bit. The communication is serialDthe trans-
mit and receive signals hold one bit at a time. Bit duration is
one baud time.
The UART can be configured with the following communica-
tion parameters: 7-bit or 8-bit data formats, with or without
parity, with one or two stop bits.
Baud rate is generated internally, by dividing CTTL under
software control. Break is generated under software control.
Break detection is via the frame error status bit (UCLST.FE).
The UART is full-duplex, it can transmit and receive charac-
ters simultaneously. The software may use either polling or
interrupts to operate the UART. Both transmission and re-
ception are double buffered to relax software response
time.
36
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