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| 型號： | NS32FX100VF |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | System Controller |
| 中文描述： | 系統(tǒng)控制器 |
| 文件頁數(shù)： | 17/94頁 |
| 文件大小： | 955K |
| 代理商： | NS32FX100VF |
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2.0 Architecture
(Continued)
2.3.4.1 Analog Transmitter
The input to the transmit analog circuit is the serial bit
stream at OSR, which is generated by DSDM. This serial bit
stream is fed to a 1-bit D/A converter. This D/A converter is
implemented by an analog switch, which selects either
a
5V
or
b
5V inputs. These voltages are filtered by an RC, low-
frequency, Low Pass Filter (LPF), to filter supply noise, and
to avoid crosstalk between the transmit and receive circuits.
The D/A output is filtered, by a three pole LPF with unity
gain, to attenuate the out-of-band quantization noise. The
output of the LPF passes through a 600
X
resistor.
2.3.4.2 Analog Receiver
The reception analog circuit obtains its analog input signal
from an isolation transformer. The signal passes through a
buffer amplifier, and then enters the Sigma Delta second
order loop. The amplifier has two gain levels. One gain level
provides a total gain of 0 dB and the second level provides
a total gain of 9 dB. The two gain level are controlled by the
GAIN signal.
The Sigma Delta second order loop contains two integrators
and a comparator to zero. The comparator output is the
SDIN input to the on-chip Sigma Delta part. SDIN is sam-
pled on-chip at OSR, is passed to the digital filters and re-
turns as feedback (SDFDBK pin) to the analog part. This
feedback enters a 1-bit D/A converter. This D/A converter
is implemented by an analog switch, which selects either
a
5V or
b
5V inputs. These voltages are filtered by an RC
low frequency LPF, to reduce supply noise, and to avoid
crosstalk between the transmit and receive circuits. The
feedback is an input to the first integrator unit.
The receiver analog circuit can be calibrated by receiving a
known reference voltage. When the circuit is calibrated, the
receiver input signal is a known reference voltage (V
REF
),
otherwise the receiver input is the input signal from the iso-
lation transformer.
2.3.5 Registers
The following is a partial list of registers. For a full list see
the detailed SD documentation, available to source-level
customers.
SDTX
Sigma-Delta Transmit Data. This register is the
transmit FIFO port. Any attempt to read from this
register will cause an unpredictable result.
SDRX
Sigma-Delta Transmit Data. This register is the re-
ceive FIFO port. Any attempt to write to this regis-
ter will cause an unpredictable result.
SDCNTL Control register
15
13
12
11
7
6
5
4
3
2
1
0
N/A
N/A
PRES
N/A
TE
N/A
RE
N/A
Upon reset SDCNTL.PRES is loaded at the minimum pre-
scale value in Full-duplex mode, ‘‘01001’’. All other imple-
mented bits of SDCNTL are cleared to ‘‘0’’.
NOTE: Bits marked N/A are available only for source-level customers. For
other customers, they must not be modified.
RE
Enables or disables receive mode.
0 : Receive mode is disabled.
1 : Receive mode is enabled.
TE
Enables or disables transmit mode.
0 : Transmit mode is disabled.
1 : Transmit mode is enabled.
PRES CTTL prescale. The SDC over-sampling rate is gen-
erated by dividing the CTTL clock by a pre-scale di-
vider. The PRES value is calculated as follows:
PRES
e
[
(CTTL/OSR) - 1
]
.
Some examples for sample rate 9.6 kHz and 8 kHz are giv-
en below:
CTTL Frequency
(Sample Rate
9.6 kHz)
CTTL Frequency
(Sample Rate
8.0 kHz)
SDCNTL.PRES
01011
01110
01111
10000
10001
10010
10011
14.7456 MHz
18.4320 MHz
19.6608 MHz
20.8896 MHz
22.1184 MHz
23.3472 MHz
24.5760 MHz
12.2880 MHz
15.3600 MHz
16.3840 MHz
17.4080 MHz
18.4320 MHz
19.4560 MHz
20.4800 MHz
SDFTM Fine Timing register.
7
4
3
2
0
res
ADV
STEP
STEP
Advance or delay steps amount (0–7)
ADV
Advance direction
0: Delay mode is enabled
1: Advance mode is enabled
Writing to this register, while SDCNTL.RE is ac-
tive, is allowed only if SDFTM.STEP is equal to a
‘‘0’’.
Writing to this register, while both SDCNTL.RE is
active and SDFTM.STEP is not ‘‘0’’, will cause an
unpredictable result.
While SDCNTL.RE is active, this register holds
the number of advance or delay steps yet to be
executed.
SDRGC
Receive Gain Control register. Used to amplify or
attenuate the receive IIR output samples. The
value to be written in SDRGC register is 128
c
10
(Gain/20)
, rounded to the nearest integer num-
ber.
Some examples are given in the following table:
Gain (dB)
SDRGC
b
18
b
17.5
0x0010
0x0011
.
.
0x0080
0x0081
.
.
0x7D98
.
.
0
0.1
.
.
48.0
17
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