
Preliminary Information
MT9071
75
14.2 E1 PCM30 Payload Data
The E1 PCM30 payload usually consists of channels 1 to 30, refer to Section 5.1 E1 Interface Overview.
14.2.1
E1 PCM30 & ST-BUS DSTi/DSTo Timeslot Relationship
When mapping to the PCM30 payload, only the time slots 1 to 15 and 17 to 31 of an ST-BUS are used. See
Table 29 - E1 PCM30 & ST-BUS DSTi/DSTo Timeslot Relationship. Note that ST-BUS timeslots 0 and 16 may
be used in numerous modes of operation including transparent mode, CAS and CCS. In addition, PCM30
channels 15,16 and 31 may be used for CCS.
15.0 Loopbacks
In order to meet PRI Layer 1 requirements and to assist in circuit fault sectionalization, the MT9071 has
numerous loopback functions. Loopback functions are enabled through control registers as detailed in Table 30
- Loopback Control Register Summary. The loopback configurations for T1 and E1 are the same and are
detailed in the following loopback descriptions.
PCM30 Timeslot
T
R
A
N
C
E
I
V
E
R
0-3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
PCM30 Channel
-
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
-
16 17 18 19 20 21 22 23
24
25
26
27
28
29
30
ST-BUS 2.048Mb/s DSTi/DSTo Timeslot
0-3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
ST-BUS 8.192Mb/s DSTi/DSTo Timeslot
0
0
4
8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124
1
1
5
9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97 101 105 109 113 117 121 125
2
2
6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126
3
3
7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 68 75 79 83 87 91 95 99 103 107 111 115 119 123 127
Table 29 - E1 PCM30 & ST-BUS DSTi/DSTo Timeslot Relationship
Loopback Type Control Bit
T1 Mode Control Register
E1 Mode Control Register
ST-BUS
Digital
Payload
Metallic
Remote
Local Timeslot
Remote
Timeslot
SLBK
DLBK
PLBK
MLBK
RLBK
LTSL
RTSL
Table 88 - T1 Loopback Control - R/W
Address Y05
Table 81 - E1 Test, Error and Loopback
Control - R/W Address Y01
Table 173 - T1 & E1 LIU Control - R/W Address YE3
Table 166 - T1 Per Channel 1 to 24
Control Registers - R/W Address Y90-
YA7
Table 167 - E1 Per Timeslot 0 to 31
Control Registers - R/W Address Y90-
YAF
Table 30 - Loopback Control Register Summary