參數(shù)資料
型號: MT9071
廠商: Mitel Networks Corporation
英文描述: Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器(集成四個獨立幀調(diào)節(jié)器))
中文描述: 四T1/E1/J1收發(fā)器(多端口的T1/E1/J1幀調(diào)節(jié)器(集成四個獨立幀調(diào)節(jié)器))
文件頁數(shù): 133/217頁
文件大?。?/td> 686K
代理商: MT9071
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Preliminary Information
MT9071
133
0
CRCIW
CRC-4 Interworking.
If one, indicates the CRC-4 interworking status is CRC-4 to CRC-4 (local
to remote). The transmit PCM30 link is framed to CRC-4 with E1 and E2 bits sent, and the
receive PCM30 link is treated as CRC-4 with E1 and E2 bits received. If zero, indicates the
CRC-4 interworking status is CRC-4 to non-CRC (local to remote). In this case, the transmit
PCM30 link is framed to CRC-4 but the E1 and E2 bits are not sent, and the receive PCM30 link
is not treated as a CRC-4 multiframe but only as a basic frame and signaling multiframe frame
only.
Table 105 - E1 Synchronization & CRC-4 Remote Status - R Address Y10
Bit
Name
Functional Description
15-3 (#### #### ####) Not Used
2
ONESEC
One Second Timer Status.
This bit toggles from low to high once every second, and is
synchronous with the applied125us frame pulse at pin FPb.
Two Second Timer Status.
This bit toggles from low to high once every two seconds,
and is synchronous with the applied125us frame pulse at pin FPb.
Not Used
Table 106 - T1 Timer Status - R Address Y11
1
TWOSEC
0
(#)
Bit
Name
Functional Description
15-14
13
(##)
Not Used
ONESEC
One Second Timer Status.
This bit toggles from low to high once every second, and is
synchronous with the applied125us frame pulse at pin FPb.
TWOSEC
Two Second Timer Status.
This bit toggles from low to high once every two seconds, and is
synchronous with the applied125us frame pulse at pin FPb.
T1
Timer 1.
If one, indicates that a receive PCM30 link with non-normal operational CRC-4
frames (CSYNC=1, see Table 105 - E1 Synchronization & CRC-4 Remote Status - R Address
Y10) has persisted for at least 100ms. This bit is zero when Timer 2 (T2 of this register) is one.
Refer to I.431 Section 5.9.2.2.3.
T2
Timer 2.
If one, indicates that a receive PCM30 link with normal operational CRC-4 frames
(CSYNC=0, see Table 105 - E1 Synchronization & CRC-4 Remote Status - R Address Y10)
has persisted for at least 10ms. This bit is cleared (zero) when non-normal operational frames
(CSYNC=1) occur. Refer to I.431 Section 5.9.2.2.3.
T400
400ms Timer Status.
This is the 400ms CRC-4 multiframe alignment timer. This bit initially
changes state from zero to one synchronously with the T8 bit (of this register) after the T8 bit
has consecutively toggled 50 times (400ms). While this condition persists (T8=0101 etc.), the
T400 bit continues to stay high (one). The T400 bit is cleared (zero) with the T8 bit when CRC-
4 multiframe synchronization is acquired (CSYNC=0, see Table 105 - E1 Synchronization &
CRC-4 Remote Status - R Address Y10).
T8
8ms Timer Status.
This is the 8ms CRC-4 multiframe alignment timer. This bit initially
changes state from zero to one synchronously with the CRCRF bit (of this register) when the
received PCM30 link CRC-4 multiframe synchronization (CSYNC = 1, see Table 105 - E1
Synchronization & CRC-4 Remote Status - R Address Y10) could not be found within the time
out period of 8 ms after detecting basic frame synchronization (BSYNC=0, see Table 105 - E1
Synchronization & CRC-4 Remote Status - R Address Y10). While this condition persists
(CRCRF=1), the T8 bit continues to change state every 8ms. The T8 bit is cleared (zero) with
the CRCRF bit when CRC-4 multiframe synchronization is acquired (CSYNC =0).
(###)
Not Used
Table 107 - E1 CRC-4 Timers & CRC-4 Local Status - R Address Y11
12
11
10
9
8
7-5
Bit
Name
Functional Description
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