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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 112/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
112
10
X2NI
(0)
E1 Transceiver 2 National Interrupt.
When any bit in the E1 Transceiver 2 - E1 National Interrupt
Status - R Address Y36 (Y=2) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 2 Counter Interrupt.
When any bit in the E1 Transceiver 2 - E1 Counter Interrupt
Status - R Address Y35 (Y=2) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 2 Sync Interrupt.
When any bit in the E1 Transceiver 2 - E1 Sync Interrupt Status
- R Address Y34 (Y=2) is set to one, this status bit is one; otherwise, it is zero. The corresponding
bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this operation to
function.
E1 Transceiver 1 HDLC Interrupt.
When any bit in the E1 Transceiver 1 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=1) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 1 National Interrupt.
When any bit in the E1 Transceiver 1 - E1 National Interrupt
Status - R Address Y36 (Y=1) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 1 Counter Interrupt.
When any bit in the E1 Transceiver 1 - E1 Counter Interrupt
Status - R Address Y35 (Y=1) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 1 Sync Interrupt.
When any bit in the E1 Transceiver 1 - E1 Sync Interrupt Status
- R Address Y34 (Y=1) is set to one, this status bit is one; otherwise, it is zero. The corresponding
bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this operation to
function.
E1 Transceiver 0 HDLC Interrupt.
When any bit in the E1 Transceiver 0 - T1 & E1 HDLC Interrupt
Status - R Address Y33 (Y=0) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 0 National Interrupt.
When any bit in the E1 Transceiver 0 - E1 National Interrupt
Status - R Address Y36 (Y=0) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 0 Counter Interrupt.
When any bit in the E1 Transceiver 0 - E1 Counter Interrupt
Status - R Address Y35 (Y=0) is set to one, this status bit is one; otherwise, it is zero. The
corresponding bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this
operation to function.
E1 Transceiver 0 Sync Interrupt.
When any bit in the E1 Transceiver 0 - E1 Sync Interrupt Status
- R Address Y34 (Y=0) is set to one, this status bit is one; otherwise, it is zero. The corresponding
bit in the E1 Interrupt Vector Mask - R/W Address 902 must be unmasked for this operation to
function.
Table 75 - E1 Interrupt Vector Status - R Address 910
9
X2CI
(0)
8
X2SI
(0)
7
X1HI
(0)
6
X1NI
(0)
5
X1CI
(0)
4
X1SI
(0)
0
X0HI
(0)
2
X0NI
(0)
1
X0CI
(0)
0
X0SI
(0)
Bit
Name
Functional Description
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