
Preliminary Information
MT9071
157
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CEL15
CEL14
CEL13
CEL12
CEL11
CEL10
CEL9
CEL8
CEL7
CEL6
CEL5
CEL4
CEL3
CEL2
CEL1
CEL0
(0000 0000
0000 0000)
CRC-6 Error Count Latch.
These bits make up a latch which samples the current value of
the corresponding counter (T1 CRC-6 Error Counter - R/W Address Y19) on the rising
edge of the internal one second timer status bit ONESEC (T1 Timer Status - R Address
Y11). CEL0 is the least significant bit (LSB). This latch is cleared with either:
a) A hard reset (RESET pin)
b) A unique soft reset (RST bit detailed in Table 178 - T1 Interrupt and I/O Control - R/W
Address YF1)
c) A global soft reset (RSTC bit detailed in Table 70 - T1 & E1 Global Mode Control - R/
W Address 900)
Table 143 - T1 CRC-6 Error Counter Latch - R Address Y2A
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CEL15
CEL14
CEL13
CEL12
CEL11
CEL10
CEL9
CEL8
CEL7
CEL6
CEL5
CEL4
CEL3
CEL2
CEL1
CEL0
CRC-4 Error Count Latch.
These bits make up a latch which samples the current value of the
corresponding counter (E1 CRC-4 Error Counter - R/W Address Y19) on the rising edge of the
internal one second timer status bit ONESEC (E1 CRC-4 Timers & CRC-4 Local Status - R
Address Y11). CEL0 is the least significant bit (LSB). This latch is cleared with either:
a) A hard reset (RESET pin)
b) A unique soft reset (RST bit detailed in Table 85 - E1 DL, CCS, CAS and Other Control - R/W
Address Y03)
c) A global soft reset (RSTC bit detailed in Table 70 - T1 & E1 Global Mode Control - R/W
Address 900)
Table 144 - E1 CRC-4 Error Count Latch - R/W Address Y2A
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
OFL7
OFL6
OFL5
OFL4
OFL3
OFL2
OFL1
OFL0
Out of Frame Alignment Counter Latch.
These bits make up a latch which samples the current
value of the corresponding counter (T1 Out of Frame and Change of Frame Counters - R/W
Address Y1A) on the rising edge of the internal one second timer status bit ONESEC (T1 Timer
Status - R Address Y11). OFL0 is the least significant bit (LSB). This latch is cleared with either:
a) A hard reset (RESET pin)
b) A unique soft reset (RST bit detailed in Table 178 - T1 Interrupt and I/O Control - R/W
Address YF1)
c) A global soft reset (RSTC bit detailed in Table 70 - T1 & E1 Global Mode Control - R/W
Address 900)
Table 145 - T1 Out of Frame & Change of Frame Counter Latch - R Address Y2B