參數(shù)資料
型號(hào): MT9071
廠商: Mitel Networks Corporation
英文描述: Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器(集成四個(gè)獨(dú)立幀調(diào)節(jié)器))
中文描述: 四T1/E1/J1收發(fā)器(多端口的T1/E1/J1幀調(diào)節(jié)器(集成四個(gè)獨(dú)立幀調(diào)節(jié)器))
文件頁(yè)數(shù): 53/217頁(yè)
文件大?。?/td> 686K
代理商: MT9071
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Preliminary Information
MT9071
53
There is a specific relationship between the read and write pointers of the receive slip buffer (see Figure 13 -
Read and Write Pointers in the E1 Slip Buffers). Measuring clockwise from the write pointer, if the read pointer
comes within 2 channels of the write pointer a frame slip will occur, which will put the read pointer 34 channels
from the write pointer. Conversely, if the read pointer moves more than 60 channels from the write pointer, a
slip will occur, which will put the read pointer 28 channels from the write pointer. This provides a worst case
hysteresis of 26 channels peak (52 channels peak-to-peak) or a wander tolerance of 416 UI peak-to-peak.
Figure 13 - Read and Write Pointers in the E1 Slip Buffers
6.2.2
E1 Receive Slip Buffer Bypass
For applications which don’t require the elastic buffer and require minimum delay, the elastic buffer may be
bypassed by using one of two methods. First, by setting the ELAS control register bit to one and using the
DSTo output, or by using the RxD pin output (regardless of the ELAS setting). These outputs contain all the
PCM30 received data after HDB3 decoding but before passing through the elastic buffer. The output data is
synchronous with the extracted clock (RxCK pin) output. Also synchronous with the RxCK pin is the basic
frame pulse provided at the RxBF pin output. This output can be used to identify the basic frame boundary of
the RxD output data.
6.3
E1 Transmit Jitter Attenuator
In E1 mode, the MT9071 contains a jitter attenuator in the LIU transmitter portion of the device.
The MT9071 meets the E1 jitter transfer characteristics as specified by ETSI and ITU-T (see Figure 19 - ETSI
Jitter Transfer and Figure 20 - ITU-T Jitter Transfer). Its intrinsic jitter is less than 0.02 UI.
The transmit jitter attenuator has data written to it from the system side 2.048 Mb/s stream. The data is clocked
out of the buffer using a dejittered 16.384Mb/s clock (8 X 2.048Mb/s) from the internal PLL. The source signal
to the PLL may be any one of the four extracted clocks (RxCK[3:0]), the external clock (ESYN), the backplane
clock (CKb), the backplane frame pulse (FPb)or the master clock (OSCi). The transmit 2.048 MHz clock is
always phase locked to one of these signals. The jitter attenuator is 128 bits deep allowing jitter and wander
(128 U.I.) to occur between the PLL output signal and the system backplane (CKb).
Two internal elements determine the jitter attenuation. This includes the PLL’s internal 1.9Hz low pass loop
filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125us. Therefore,
if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum
output phase slope will be limited (i.e. attenuated) to 5ns/125us.
The jitter attenuator should only be necessary if timing is derived from the ST-BUS signals applied to the CKb
and FPb pins and these signals contain jitter and wander in excess of the required amounts desired for
transmission on the PCM30 link.
Write Pointer
60 CH
2 CH
47 CH
15 CH
34 CH
28 CH
512 Bit
Elastic
Store
+26 CH
-26 CH
Wander Tolerance
Read Pointer
Read Pointer
Read Pointer
Read Pointer
5
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