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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 92/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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4-4
Power Considerations
In Single master mode with the DLL disabled (that is, the DLLDIS bit in the Hard Reset Configuration
Word is set), the following connections should be used:
— Connect the oscillator output through a buffer to CLKIN.
— Connect DLLIN to GND (pull low).
— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using
the following guidelines:
°
The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.
°
The maximum load on CLKOUT must not exceed 10 pF.
°
Use a zero-delay buffer with a jitter less than 0.3 ns.
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected.
Otherwise, it should be pulled up.
The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and
BM[0–2]
are used to configure the MSC8102 and are sampled on the deassertion of the PORESET
signal. Therefore, they should be tied to GND or VDD either directly or through a pull-down or a pull-up
resistor until the deassertion of the PORESET signal.
The BR, BG, DBG, EXT_BR[2–3], EXT_BG[2–3], EXT_DBG[2–3], and TS must be pulled up if the
BCR[EBM] bit is set.
When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full
drive) signals must be pulled up.
Note:
For details on configuration, see the MSC8102 User’s Guide and MSC8102 Reference Manual.
4.4 Power Considerations
The internal power dissipation consists of three components:
PINT = PTCORE + PSIU + PBUSES + PPERIPH
The power dissipation depends on the operating frequency of the different portions of the chip. To
determine the power dissipation at a given frequency, the following equations should be applied:
PCORE (fc) = ((PCORE – PLCO)/275) × fc + PLCO
PTCORE (fc) = (PCORE × 4)
PSIU (fc) = ((PSIU – PLSI)/91.67) × fc + PLSI
PPERIPH (fc) = ((PPERIPH – PLPE)/91.67) × fc + PLPE
PBUSES (fc) = PBUSES /91.67 × fc
Where,
fc is the operating frequency in MHz and all power numbers are in mW
PLCO is the SC140 Core leakage power
PLSI is the SIU leakage power
PLPE is the peripheral leakage power
To determine a total power dissipation in a specific application, the following equation should be applied
for each I/O output pin:
Equation 3: P = C
× V
DDH
2
× f
s × 10
–3
Where:
P = power in mW
C = load capacitance in pF
fs = output switching frequency in MHz.
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