參數(shù)資料
型號(hào)： MSC8102M4000
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 7/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
1-7
Direct Slave Interface, System Bus, and Interrupt Signals
A[0–31]
Input/
Output
Address Bus
When the MSC8102 is in external master bus mode, these pins function as the system
address bus. The MSC8102 drives the address of its internal bus masters and responds to
addresses generated by external bus masters. When the MSC8102 is in internal master
bus mode, these pins are used as address lines connected to memory devices and are
controlled by the MSC8102 memory controller.
TT0
Input/
Output
Bus Transfer Type 0
The bus master drives this pins during the address tenure to specify the type of the
transaction.
TT1
Input/
Output
Bus Transfer Type 1
The bus master drives this pins during the address tenure to specify the type of the
transaction. Some applications use only the TT1 signal, for example, from MSC8102 to
MSC8102 or MSC8102 to MSC8101 and vice versa. In these applications, TT1 functions
as read/write signal.
TT[2–4]
CS[5–7]
Input/
Output
Bus Transfer Type 2–4
The bus master drives these pins during the address tenure to specify the type of the
transaction.
Chip Select 5–7
Enables specific memory devices or peripherals connected to the system bus.
CS[0–4]
Output
Chip Select 0–4
Enables specific memory devices or peripherals connected to the system bus.
TSZ[0–3]
Input/
Output
Transfer Size 0–3
The bus master drives these pins with a value indicating the number of bytes transferred in
the current transaction.
TBST
Input/
Output
Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst
transaction (transfers eight words).
IRQ1
GBL
Input
Output
Interrupt Request 11
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Global
1
When a master within the MSC8102 initiates a bus transaction, it drives this pin. Assertion
of this pin indicates that the transfer is global and should be snooped by caches in the
system.
IRQ3
BADDR31
Input
Output
Interrupt Request 31
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Burst Address 31
1
There are five burst address output pins, which are outputs of the memory controller.
These pins connect directly to burstable memory devices without internal address
incrementors controlled by the MSC8102 memory controller.
IRQ2
BADDR30
Input
Output
Interrupt Request 21
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Burst Address 30
1
There are five burst address output pins, which are outputs of the memory controller.
These pins connect directly to burstable memory devices without internal address
incrementors controlled by the MSC8102 memory controller.
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
Type
Description
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