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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 37/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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2-12
AC Timings
2.6.5 DSI Timing
The timings in the following sections are based on a 30 pF capacitive load. See Section 2.6.1, Load
Assumptions, on page 3 for more details.
2.6.5.1 DSI Asynchronous Mode
Table 2-14. DSI Asynchronous Mode Timing
No.
Characteristics
Min
Max
Unit
100
Attributes1 setup time before strobe (HWBS[n]) assertion
2.3
—
ns
101
Attributes1 hold time after data strobe deassertion
2.0
—
ns
102
Read/Write data strobe deassertion width
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
1.8 + TREFCLK
5 + TREFCLK
5 + (1.5
× T
REFCLK)
5 + (2.5
× T
REFCLK)
1.8 + TREFCLK
—
ns
103
Read data strobe deassertion to output data high impedance
—
11.5
ns
104
Read data strobe assertion to output data active from high impedance
2.7
—
ns
105
Output data hold time after read data strobe deassertion
3.0
—
ns
106
Read/Write data strobe assertion to HTA active from high impedance
2.5
—
ns
107
Output data valid to HTA assertion
4.0
—
ns
108
Read/Write data strobe assertion to HTA valid2
—7.5
ns
109
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
—7.5
ns
110
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
—7.2
ns
111
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
—
5 + TREFCLK
5 + (1.5
× T
REFCLK)
5 + (2.5
× T
REFCLK)
ns
112
Read/Write data strobe assertion width
1.8 + TREFCLK
—ns
201
Host data input setup time before write data strobe deassertion
1.7
—
ns
202
Host data input hold time after write data strobe deassertion
3.2
—
ns
Notes:
1.
Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2.
This specification is tested in dual strobe mode. Timing in single strobe mode is guaranteed by design.
3.
All values listed in this table are tested or guaranteed by design.
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