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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 31/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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2-7
AC Timings
Table 2-10. Timing for a Reset Configuration Write through the DSI or System Bus
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
CLKIN = 33 MHz
CLKIN = 75 MHz
16/CLKIN
484.8
213.3
—ns
2
Delay from deassertion of external PORESET to deassertion of internal
PORESET
CLKIN = 33 MHz
CLKIN = 75 MHz
1024/CLKIN
31.03
13.65
s
3
Delay from de-assertion of internal PORESET to SPLL lock
CLKIN = 33 MHz
CLKIN = 75 MHz
800/(CLKIN/PDF)
(pre-division factor)
48.5
32.0
s
4
Delay from SPLL lock to DLL lock.
DLL enabled
REFCLK = 33 Mhz
REFCLK = 75 Mhz
DLL disabled
3073/REFCLK
—
93.12
40.97
0.0
s
5
Delay from SPLL and DLL lock to HRESET de-assertion
DLL enabled
REFCLK = 33 Mhz
REFCLK = 75 Mhz
DLL disabled
REFCLK = 33 Mhz
REFCLK = 75 Mhz
3585/REFCLK
512/REFCLK
108.64
47.5
15.52
6.83
s
6
Delay from SPLL and DLL lock to SRESET de-assertion
DLL enabled
REFCLK = 33 Mhz
REFCLK = 75 Mhz
DLL disabled
REFCLK = 33 Mhz
REFCLK = 75 Mhz
3588/REFCLK
515/REFCLK
108.73
47.84
15.61
6.87
s
Note:
Timings are not tested, but are guaranteed by design.
Figure 2-1. Timing Diagram for a Reset Configuration Write
PORESET
Internal
HRESET
Input
Output (I/O)
SRESET
Output (I/O)
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1-2]
Host programs
Word
SPLL and DLL are locked
(no external indication)
PORESET
Reset Configuration
pins are sampled
1
2
MODCK[3–5],
are ready for SPLL.
DLLDIS bits
1 + 2
3 + 4
5
6
When DLL is disabled,
reset period is shortened
by 3073 bus clocks.
SPLL and DLL
locking period.
Reset configuration write
sequence occurs during this
period.
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