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參數(shù)資料
| 型號(hào)： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 24/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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1-22
EOnCE Event and JTAG Test Access Port Signals
1.7 EOnCE Event and JTAG Test Access Port Signals
The MSC8102 uses two sets of debugging signals for the two types of internal debugging modules:
EOnCE and the JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all
accessed externally by the same two signals EE0 and EE1. The MSC8102 supports the standard set of
Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan
Architecture specification and described in Table 1-8.
1.8 Reserved Signals
Table 1-8. JTAG Test Access Port Signals
Signal Name
Type
Signal Description
EE0
Input
EOnCE Event Bit 0
Used for putting the internal SC140 cores into Debug mode.
EE1
Output
EOnCE Event Bit 1
Indicates that at least one on-chip SC140 core is in Debug mode.
TCK
Input
Test Clock—A test clock signal for synchronizing JTAG test logic.
TDI
Input
Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on
the rising edge of TCK and has an internal pull-up resistor.
TDO
Output
Test Data Output—A test data serial signal for test instructions and data. TDO can be
tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and
changes on the falling edge of TCK.
TMS
Input
Test Mode Select—Sequences the test controller’s state machine, is sampled on the
rising edge of TCK, and has an internal pull-up resistor.
TRST
Input
Test Reset—Asynchronously initializes the test controller, has an internal pull-up resistor,
and must be asserted after power up.
Table 1-9. Reserved Signals
Signal Name
Type
Signal Description
TEST
Input
Test
Used for manufacturing testing. You must connect this pin to GND.
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