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參數資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數： | 9/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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1-9
Direct Slave Interface, System Bus, and Interrupt Signals
ARTRY
Input/
Output
Address Retry
Assertion of this signal indicates that the bus master should retry the bus transaction. An
external master asserts this signal to enforce data coherency with its caches and to
prevent deadlock situations.
D[0–31]
Input/
Output
Data Bus Bits 0–31
In write transactions, the bus master drives the valid data on this bus. In read transactions,
the slave drives the valid data on this bus.
Reserved
DP0
DREQ1
EXT_BR2
Input
Input/
Output
Input
The primary configuration selection (default after reset) is reserved.
System Bus Data Parity 0
The agent that drives the data bus also drives the data parity signals. The value driven on
the data parity 0 pin should give odd parity (odd number of ones) on the group of signals
that includes data parity 0 and D[0–7].
DMA Request 1
Used by an external peripheral to request DMA service.
External Bus Request 2
An external master asserts this pin to request bus ownership from the internal arbiter.
IRQ1
DP1
DACK1
EXT_BG2
Input
Input/
Output
Interrupt Request 1
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
System Bus Data Parity 1
The agent that drives the data bus also drives the data parity signals. The value driven on
the data parity 1 pin should give odd parity (odd number of ones) on the group of signals
that includes data parity 1 and D[8–15].
DMA Acknowledge 1
The DMA drives this output to acknowledge the DMA transaction on the bus.
External Bus Grant 22
The MSC8102 asserts this pin to grant bus ownership to an external bus master.
IRQ2
DP2
DACK2
EXT_DBG2
Input
Input/
Output
Interrupt Request 2
One of fifteen external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
System Bus Data Parity 2
The agent that drives the data bus also drives the data parity signals. The value driven on
the data parity 2 pin should give odd parity (odd number of ones) on the group of signals
that includes data parity 2 and D[16–23].
DMA Acknowledge 2
The DMA drives this output to acknowledge the DMA transaction on the bus.
External Data Bus Grant 22
The MSC8102 asserts this pin to grant data bus ownership to an external bus master.
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
Type
Description
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MSC8102M4400 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8102RM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8102UG | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8103 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MSC8103/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
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