參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 1/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
Technical Data
MSC8102/D
Rev. 6, 10/2003
Quad Core 16-Bit
Digital Signal Processor
Figure 1. MSC8102 Block Diagram
MQBus
SQBus
Local Bus
128
Boot
ROM
64
PLL
JTAG
RS-232
Internal Local Bus
Internal System Bus
IPBus
IP Master
64
UART
Memory
Controller*
M2
RAM
GPIO Pins
Interrupts
Memory
Controller*
System Bus
32/64
DSI Port
32
32/64
PLL/Clock
JTAG Port
SC140
Extended Core
SC140
Extended Core
SC140
Extended Core
System
Interface
32 Timers
4 TDMs
SC140
Extended Core
DMA
60x-compatible
Bridge
SIU
Registers
Direct
Slave
Interface
(DSI)
8 Hardware
Semaphores
GIC
GPIO
*There is a single memory controller that controls access to both the local bus and the system bus.
The raw processing
power of this highly
integrated system-on-
a-chip device enables
developers to create
next generation
networking products
that offer tremendous
channel densities, while
maintaining system
flexibility, scalability,
and upgradeability. The
MSC8102 is offered in
two core speed levels:
250 and 275 MHz.
The MSC8102 is a highly integrated system-on-
a-chip that combines four StarCore SC140
extended cores with an RS-232 serial interface,
four time-division multiplexed (TDM) serial
interfaces, thirty-two general-purpose timers, a
flexible system interface unit (SIU), and a
multi-channel DMA engine. The four extended
cores can deliver a total 4400 DSP MMACS
performance at 275 MHz.
Each core has four arithmetic logic units (ALUs),
internal memory, a write buffer, and two interrupt
controllers. The MSC8102 targets high-bandwidth
highly computational DSP applications and is
optimized for wireless transcoding and packet
telephony as well as high-bandwidth base station
applications. The MSC8102 delivers enhanced
performance while maintaining low power
dissipation and greatly reduces system cost.
What’s New?
References to
preliminary information
were removed. A note
was added to the DLLIN
signal in Table 1-3.
Specifications were
updated in Table 2-2
Additional information
was signal connections
for single master mode
with the DLL disabled in
Section 4.3. Numbers
were added to the
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