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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 32/96頁 |
| 文件大小： | 1557K |
| 代理商： | MSC8102M4000 |
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2-8
AC Timings
2.6.4 System Bus Access Timing
2.6.4.1 Core Data Transfers
Generally, all MSC8102 bus and system output signals are driven from the rising edge of the reference
clock (REFCLK). The REFCLK is either the DLLIN signal or, if DLL is disabled, the CLKOUT signal.
Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and
T3 at the falling edge), as Figure 2-2 shows.
Figure 2-2 is a graphical representation of the internal ticks.
The UPM machine and GPCM machine outputs change on the internal tick determined by the memory
controller programming, the AC specifications are relative to the internal tick. SDRAM machine outputs
change only on the REFCLK rising edge.
Figure 2-2. Internal Tick Spacing for Memory Controller Signals
Table 2-11. AC Timing for SIU Inputs
No.
Characteristic
Value2 Units
10
Hold time for all signals after the 50% level of the REFCLK rising edge
1
ns
11a
ARTRY/ABB/TS setup time before the 50% level of the REFCLK rising edge
4.5
ns
11b
DBG/DBB/BG/BR/TC setup time before the 50% level of the REFCLK rising edge
4.5
ns
11c
AACK setup time before the 50% level of the REFCLK rising edge
5.0
ns
11d
TA/TEA/PSDVAL setup time before the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
4.5
5.0
ns
12
Data bus setup time before REFCLK rising edge in Normal mode
Pipeline mode
Non-pipeline mode
3.0
5.0
ns
13
Data bus setup time before the 50% level of the REFCLK rising edge in ECC and
PARITY modes
Pipeline mode
Non-pipeline mode
4
7
ns
14
DP setup time before the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
5.0
6.5
ns
15a
Address bus setup time before the 50% level of the REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
4.0
8.0
ns
15b
Address attributes: TT/TBST/TSIZ/GBL setup time before the 50% level of the
REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
6.0
9.0
ns
161
PUPMWAIT signal setup time before the 50% level of the REFCLK rising edge
5.0
ns
Notes:
1.
Synchronous operation. Asynchronous operation may have a higher setup time.
2.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK
rising edge.
REFCLK
T1
T2
T3
T4
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