- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45388 > MSC8102M4000 (MOTOROLA INC) 32-BIT, 75 MHz, OTHER DSP, CBGA431 PDF資料下載
參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 30/96頁 |
| 文件大小： | 1557K |
| 代理商： | MSC8102M4000 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
2-6
AC Timings
2.6.3.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least
16 CLKIN cycles after external power to the MSC8102 reaches at least 2/3 VDD.
2.6.3.2 Reset Configuration
The MSC8102 has two mechanisms for writing the reset configuration:
Through the direct slave interface (DSI), or
Through the system bus
When reset configuration written through the system bus, the MSC8102 uses as a configuration master or
as a configuration slave. If a configuration slave is selected, but no special configuration word is written,
a default configuration word is applied. Fourteen signal levels (see Chapter 1 for signal description
details) are sampled on PORESET deassertion to define the Reset Configuration Mode and boot and
operating conditions:
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
2.6.3.3 Reset Timing Tables
Table 2-10 and Figure 2-1 describe the reset timing for a reset configuration write through the direct
slave interface (DSI) or through the system bus.
Table 2-9. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On
Reset
(PORESET)
Hard Reset
(HRESET)
Soft Reset (SRESET)
External only
External or
Internal
(Software
Watchdog or
Bus Monitor)
External
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration Pins Sampled (Refer to Section 2.6.3.1 for details).
Yes
No
SPLL and DLL States Reset
Yes
No
System Reset Configuration write through the DSI
Yes
No
System Reset Configuration write though the System Bus
Yes
No
HRESET Driven
Yes
No
SIU Registers reset
Yes
No
IPBus Modules Reset (TDM, UART, Timers, DSI, IPBus Master,
GIC, HS, and GPIO)
Yes
SRESET Driven
Yes
Depends on command
SC140 Extended Cores Reset
Yes
MQBS Reset
Yes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSC8122TVT6400 | 32-BIT, 400 MHz, OTHER DSP, PBGA431 |
| MSC8122TVT4800V | 32-BIT, 300 MHz, OTHER DSP, PBGA431 |
| MSC8122MP8000 | 32-BIT, 500 MHz, OTHER DSP, PBGA431 |
| MSC8144ETVT800B | 133 MHz, OTHER DSP, PBGA783 |
| MSC8144EVT1000A | 133 MHz, OTHER DSP, PBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8102M4400 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8102RM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8102UG | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8103 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MSC8103/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。