參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 33/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
2-9
AC Timings
Table 2-12. AC Timing for SIU Outputs
No.
Characteristic
Value1
Units
30 pF
50 pF
30
Min delay from the 50% level of the REFCLK for all signals
1.0
ns
31
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
7.0
7.5
8.5
9.0
ns
32a
Address bus max delay from the 50% level of the REFCLK rising edge
Multi Master mode (SIUBCR[EBM] = 1)
Single Master mode (SIUBCR[EBM] = 0)
8.0
6.0
9.5
7.5
ns
32b
Address attributes: TT/TC/TBST/TSIZ/GBL max delay from the 50% level of
the REFCLK rising edge
5.8
7.3
ns
32c
BADDR max delay from the 50% level of the REFCLK rising edge
6.0
7.5
ns
33a
Data bus max delay from the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
6.0
7.5
9.0
ns
33b
DP max delay from the 50% level of the REFCLK rising edge
Pipeline mode
Non-pipeline mode
7.0
7.5
8.5
9.0
ns
34
Memory controller signals/ALE max delay from the 50% level of the
REFCLK rising edge
6.0
7.5
ns
35a
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising edge
6.5
8.0
ns
35b
AACK/ABB/TS/CS max delay from the 50% level of the REFCLK rising
edge
6.5
8.0
ns
Notes:
1.
Values are measured from the 50% level of the REFCLK rising edge to the TTL signal level (0.8/ 2 V)
2.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8102 device, the frequency is determined by
adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF
output capacitance.
In single-master mode, the frequency depends on the timing of the devices connected to the
MSC8102.
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