參數(shù)資料
型號： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁數(shù)： 36/96頁
文件大小： 1557K
代理商： MSC8102M4000
2-11
AC Timings
2.6.4.2 DMA Data Transfers
Table 2-13 describes the DMA signal timing.
The DREQ
signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral
should assert DREQ according to the timings in Table 2-13. Figure 2-4 shows synchronous peripheral
interaction.
Table 2-13. DMA Signals
No.
Characteristic
Minimum Maximum
Units
37
DREQ setup time before the 50% level of the falling edge of REFCLK
6
—
ns
38
DREQ hold time after the 50% level of the falling edge of REFCLK
0.5
—
ns
39
DONE setup time before the 50% level of the rising edge of REFCLK
7
—
ns
40
DONE hold time after the 50% level of the rising edge of REFCLK
0.5
—
ns
41
DACK/DRACK/DONE delay after the 50% level of the REFCLK rising
edge
0.5
9
ns
Figure 2-4. DMA Signals
REFCLK
DREQ
DONE
DACK/DONE/DRACK
37
38
40
39
41
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