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參數(shù)資料
| 型號： | MCC501RX200TD0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838 |
| 封裝： | BGA-838 |
| 文件頁數(shù)： | 97/102頁 |
| 文件大?。?/td> | 1929K |
| 代理商： | MCC501RX200TD0B |
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January 21, 2002— Preliminary Version
C-Port Confidential
94
INDEX: E
Gigabit Ethernet (TBI) Timing 74
Low Speed Serial Interface Timing 81
MDIO Serial Interface Timing 80
OC-3 Timing 76
PCI Timing 78
Pinout 22
PROM Interface 36
PROM Interface Timing 82
QMU Timing 87
Signal Groups in BMU Timing 86
Signal Groups in QMU Timing 88
Signal Groups in TLU Timing 87
System Clock Timing 70
TLU Timing 86
Diagram, Block
C-5 Network Processor 15
DS1/DS3 Ethernet Timing Description 72
DS1/DS3 Ethernet Timing Diagram 72
DS1/DS3 Timing Specifications 72
DS1/T1 Framer Interface Configuration 26
DS1/T1 Framer Interface Signals 26
E
Electrical Specifications 63
Absolute Maximum Ratings 63
Executive Processor 17
PCI 17
PROM Interface 17
Serial Bus Interface 17
System Interface Signals 33
System Interfaces 17
Executive Processor Timing Specifications 78
F
Fabric Interface Pin Mapping
Power X Mode 40
PRIZMA Mode 40
Utopia2/Utopia3 ATM Mode 39
Utopia2/Utopia3 PHY Mode 39
Fabric Processor 18
Fabric Processor Interface Signals 38
Fabric Processor Timing Description 84
Fabric Processor Timing Diagram 83
Fabric Processor Timing Specifications 83
Functional Description 15
G
General System Interface Signal 37
Gigabit Ethernet (GMII) Configuration 27
Gigabit Ethernet (GMII) Signals
One Cluster Example 28
Gigabit Ethernet (TBI) Timing Description 75, 75
Gigabit Ethernet (TBI) Timing Diagram 74
Gigabit Ethernet and FibreChannel TBI Configuration 29
Gigabit Ethernet and FibreChannel TBI Signals
Example 30
Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 74
GMII/TBI Transmit and Receive Pin Configurations 28
I
IDcode Register 60
Instruction Register Instructions 61
J
JTAG Data Registers 59
JTAG Identification Code and Its Sub-components 60
JTAG Instruction Register 61
JTAG Internal Register Descriptions 59
JTAG Support
L
Low Speed Serial Interface Timing Description 81
Low Speed Serial Interface Timing Diagram 81
Low Speed Serial Interface Timing Specifications 81
LVPECL Specifications 23
LVTTL Specifications 23
M
MDIO Serial Interface Timing Description 80
MDIO Serial Interface Timing Diagram 80
MDIO Serial Interface Timing Specifications 80
Measurements
C-5 Network Processor 91
Mechanical Specifications 89
Miscellaneous Test Signals for JTAG, Scan, and Internal Test
Routines 48
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