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參數(shù)資料
| 型號： | MCC501RX200TD0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838 |
| 封裝： | BGA-838 |
| 文件頁數(shù)： | 29/102頁 |
| 文件大?。?/td> | 1929K |
| 代理商： | MCC501RX200TD0B |
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January 21, 2002— Preliminary Version
C-Port Confidential
32
CHAPTER 2: SIGNAL DESCRIPTIONS
SONET OC-12 Transceiver Interface Configuration
SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a
CP within a cluster spends half its time performing receive functions, and the other half
performing transmit functions. Table 11 shows a CP Cluster configured for one OC-12
interface.
Table 11 OC-12 Signals Example
Signal Name* Pin #
Total Type
I/O
Label
Signal Description
CPn_0
1
LVTTL
O
TCLK
Deskewed Transmit Clock (77.76MHz). This clock is used to
synchronize the transmit data.
CPn_1
1
LVTTL
I
TCLK1
Transceiver Transmit Clock. This clock sets the frequency of the
transmit data and is typically sourced by the PHY chip.
CPn_2
1
LVTTL
O
TXD(0)
Transmit Data (byte-wide data, least significant bit)
CPn_3
1
LVTTL
O
TXD(1)
Transmit Data
CPn_4
1
LVTTL
O
TXD(2)
Transmit Data
CPn_5
1
LVTTL
O
TXD(3)
Transmit Data
CPn_6
1
LVTTL
0
00F
Out of Frame
CPn+1_0
1
nc
CPn+1_1
1
nc
CPn+1_2
1
LVTTL
O
TXD(4)
Transmit Data
CPn+1_3
1
LVTTL
O
TXD(5)
Transmit Data
CPn+1_4
1
LVTTL
O
TXD(6)
Transmit Data
CPn+1_5
1
LVTTL
O
TXD(7)
Transmit Data (byte-wide data, most significant bit)
CPn+1_6
1
nc
CPn+2_0
1
nc
CPn+2_1
1
LVTTL
I
RCLK
Receive Clock (77.76MHz)
CPn+2_2
1
LVTTL
I
RXD(0)
Receive Data (byte-wide receive data, least significant bit)
CPn+2_3
1
LVTTL
I
RXD(1)
Receive Data
CPn+2_4
1
LVTTL
I
RXD(2)
Receive Data
CPn+2_5
1
LVTTL
I
RXD(3)
Receive Data
CPn+2_6
1
LVTTL
I
FP
Frame Synchronization Pulse. This is valid during the third A2 of
the receive SONET frame.
CPn+3_0
1
nc
CPn+3_1
1
nc
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