參數(shù)資料
型號(hào)： MCC501RX200TD0B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838
封裝： BGA-838
文件頁數(shù)： 35/102頁
文件大?。?/td> 1929K
代理商： MCC501RX200TD0B
January 21, 2002— Preliminary Version
C-Port Confidential
38
CHAPTER 2: SIGNAL DESCRIPTIONS
Fabric Processor
Interface Signals
The FP consists of two logical signal interfaces: a receive data interface and a transmit
data interface, each with its own control and clocking signals. The interface has the
following characteristics:
The interface clocks FRXCLK and FTXCLK can have a different frequency from the core
C-5 NP clock frequency. The Fabric Data Processor (FDP) has synchronizing FIFOs at its
interface boundary to allow for a fabric interface frequency from 10MHz to 110MHz.
The receive clock FRXCLK and the transmit clock FTXCLK must share the same
frequency. The synchronization logic internal to the FP requires related clock domains
on the transmit and receive interfaces. Each of the two clocks can have different phase
alignment, however, because they are generated externally.
Each data bus can be run at widths of 16 or 32 bits of data (FIN0 - FIN31 and FOUT0 -
FOUT31) per clock. The extra data pins in each configuration remain unused. The output
pins are driven to a known state, and the input pins should also be pulled to a known
state.
Table 15 General System Interface Signal
Signal Name
Pin #
Total
Type
I/O
Signal Description
XPUHOT
J19
1
LVTTL
I
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low
equals reset and High equals active. During normal operation, this is an
external interrupt.
Total Pins
1
Table 16 Fabric Interface Signals
Signal Name
Pin #
Total
Type
I/O
Signal Description
FIN0 - FIN31
W2, V1, T1, V2, U2, V3, T3, T2, W4, V4, V5, U4, T4,
W6, V6, U6, T5, T6, V7, T7, X8, W8, V8, V9, U8, X9,
V10, U10, X10, W10, X11, V11
32
LVTTL
I
Fabric Data Bus In
FOUT0 - FOUT31
W28, V29, T29, V28, U28, V27, T27, T28, W26,
V26, V25, U26, T26, W24, V24, U24, T25, T24,
V23, T23, X22, W22, V22, V21, U22, X21, V20,
U20, X20, W20, X19, V19
32
LVTTL
O
Fabric Data Bus Out
FRXCLK
W14
1
LVTTL
I
Receive Clock
FTXCLK
W16
1
LVTTL
I
Transmit Clock
FRXCTL0 - FRXCTL6
U12, W12, V12, X12, X13, V13, X14
7
LVTTL
I, O
Receive Control Signals
FTXCTL0 - FTXCTL6
U18, W18, V18, X18, X17, V17, X16
7
LVTTL
I, O
Transmit Control Signals
Total Pins
80
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