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參數(shù)資料
| 型號(hào)： | MCC501RX200TD0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838 |
| 封裝： | BGA-838 |
| 文件頁數(shù)： | 20/102頁 |
| 文件大?。?/td> | 1929K |
| 代理商： | MCC501RX200TD0B |
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January 21, 2002— Preliminary Version
C-Port Confidential
24
CHAPTER 2: SIGNAL DESCRIPTIONS
CP Interface Signals
The C-5 NP’s 16 CPs support various network physical interfaces, providing a serial
interface to the PHY layer. Interfaces are configured via bits in the C-5 NP register set.
Many interfaces are possible by programming the configuration registers. CPs can be
used individually or in a cluster (four CPs) to implement the various interfaces.
Table 4 provides a quick reference of all the CP pins organized by clusters. There are seven
physical I/O pins associated with each CP. All pins are capable of receiving data, with some
configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can
be configured as differential pairs for LVPECL compatibility.
In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally
configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four
CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for
receive and four for transmit) or four CPs that share the transmit and receive functions for
non-wire speed applications.
During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial
Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the
SDPs, with each getting access to the necessary I/O pins.
The signals for the following CP physical interfaces are included in this section:
CCLK6
K14
1
LVTTL
I
125MHZ_CLK (Gigabit Ethernet)
CCLK7
K16
1
LVTTL
I
155_52MHZ_CLK (OC-3)
CPREF
L13
1
LVPECL
I
Reference
Total
11
* SCLK and SCLKX must not be AC-coupled.
The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP. Clock inputs associated with a
specific protocol should be wired to ground when that protocol is not used by the C-5 NP. It is also possible
to use one or more CCLKn inputs for other frequencies. Contact your C-Port representative for more
information.
If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must
be wired to an external reference, as specified in Table 34 on page 65. If none of the CPs are configured for
LVPECL operation, then the CPREF pin can be left unconnected. It is acceptable to tie the CPREF pin high or
low through a resistor, or into the specified reference, but this is not required.
Table 3 Clock and Reference Signals (continued)
Signal Name
Pin #
Total
Type
I/O
Signal Description
相關(guān)PDF資料 |
PDF描述 |
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| MCC5E0RX266WB0B | 266 MHz, RISC PROCESSOR, CBGA840 |
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| MCF5206FT33 | 32-BIT, 33.33 MHz, RISC PROCESSOR, PQFP160 |
| MCF5206FT25 | 32-BIT, 25 MHz, RISC PROCESSOR, PQFP160 |
| MCF5206FT16 | 32-BIT, 16.67 MHz, RISC PROCESSOR, PQFP160 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MCC50M10 | 制造商:Thomas & Betts 功能描述:METRIC CONNECTOR 50MMSQ M10 STUD |
| MCC50M12 | 制造商:Thomas & Betts 功能描述:METRIC CONNECTOR 50MMSQ M12 STUD |
| MCC50M14 | 制造商:Thomas & Betts 功能描述:METRIC CU CONNECTOR 50SQMM M14 STUD |
| MCC50M16 | 制造商:Thomas & Betts 功能描述:METRIC CU CONNECTOR 50SQMM M16 STUD |
| MCC50M6 | 制造商:Thomas & Betts 功能描述:METRIC CONNECTOR 50MMSQ M6 STUD |
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