
C-Port Confidential
Preliminary Version — January 21, 2002
Pin Descriptions Grouped by Function
45
QMU SRAM Interface
Signals
The QMU signals are described in Table 24. The QMU’s clock frequency is 1/ 2 the internal
core clock frequency.
Power Supply Signals
Power supply and ground signals are described in
Table 25 and their pinouts are shown in
Table 24 QMU SRAM Interface Signals
Signal Name
Pin #
Total Type
I/O* Signal Description
QCPAR
A10
1
nc
Not used
QCLK
G12
1
LVTTL
O
Clock Signal to the memory ICs
QCMD0 - QCMD15
B10, C10, D10, E10, F10, B11, D11, F11,
A12, B12, C12, D12, E12, B13, D13, F13
16
LVTTL
O
Memory Address [15: 0] to the memory
ICs
QDPAR
A8
1
LVTTL
I/O
Data parity
QDATA0 - QDATA31
D1, F1, F2, B2, C2, D2, E2, B3, D3, F3, A4,
B4, C4, D4, E4, F4, B5, D5, F5, A6, B6, C6,
D6, E6, F6, B7, D7, F7, C8, D8, E8, F8
32
LVTTL
I/O
Memory Data
QSFLOW
B9
1
LVTTL
O
Not Used
QXCTRL0
D9
1
LVTTL
O
Rd/Wr (Read is true high, write is true low)
QXCTRL1
F9
1
LVTTL
O
Memory Address [16] to the memory ICs
QXRQST
B8
1
nc
Reserved
Note: Requires Pullup or Pulldown.
Total Pins
55
*During normal (non-scan) operation.
Table 25 Power Supply Signals
Signal Name
Pin #
Total
Type
Signal Description
VDD
A3, A11, A15, A23, A27, C1, C5, C13, C17, C25, C29,
E3, E7, E15, E19, E27, G5, G9, G17, G21, G29, I7, I11,
I19, I23, J12, K1, K9, K13, K21, K25, L14, M3, M11,
M15, M23, M27, O1, O5, O13, O17, O25, O29, Q3, Q7,
Q15, Q19, Q27, S5, S9, S17, S21, S29, U7, U11, U19,
U23, W1, W9, W13, W21, W25, Y3, Y11, Y15, Y23, Y27,
AA1, AA5, AA13, AA17, AA25, AA29, AC3, AC7, AC15,
AC19, AC27
78
P
Core Supply Voltage (1.8V Input)
VDD33
A7, A19, C9, C21, E11, E23, F12, G1, G13, G25, H14, I3,
I15, I27, J16, K5, K17, K29, M7, M19, O9, O21, Q11,
Q23, S1, S13, S25, U3, U15, U27, W5, W17, W29, Y7,
Y19, AA9, AA21, AC11, AC23
39
P
I/O Supply Voltage (3.3V Input)