參數(shù)資料
型號(hào)： MCC501RX200TD0B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838
封裝： BGA-838
文件頁(yè)數(shù)： 66/102頁(yè)
文件大?。?/td> 1929K
代理商： MCC501RX200TD0B
January 21, 2002 — Preliminary Version
C-Port Confidential
66
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Power Sequencing
The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated
for periods up to one second, as is typical during power sequencing, as long as:
The VDD is not clamped to ground or some other low voltage.
The number of power cycling events averages to less than once per day over the
lifetime of the product.
It is intended that the VDD and VDD33 rail be sequenced to their final value together for
most applications.
It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running
or begin running during power sequencing to propagate reset inside the C-5 NP. Figure 9
indicates the relationship between the clocks and PRSTX. There is no requirement that the
asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be
asserted within 100
s of power initiation. Typically, reset is held low during power
initiation.
Figure 9 Bringup Clock Timing Diagram
TCLKI, PCLK,
SCLK, SCLKX,
MDCLK, FTXCLK,
FRXCLK
PRSTX
1ms
100
s
(
)
≤100
s
VDD, VDD33
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