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參數(shù)資料
| 型號： | MCC501RX200TD0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838 |
| 封裝： | BGA-838 |
| 文件頁數(shù)： | 32/102頁 |
| 文件大?。?/td> | 1929K |
| 代理商： | MCC501RX200TD0B |
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C-Port Confidential
Preliminary Version — January 21, 2002
Pin Descriptions Grouped by Function
35
of the devices connected to the bus must have either an open-drain or open-collector in
order to perform the wired-AND function required for its arbitration mechanism.
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-5 NP to communicate
through external logic to PROM. The PROM clock is 1/
2 to
1/
16 the core clock rate. The
maximum PROM size is 4MBytes x 16, and configuration is required. The PROM signals are
listed in Table 14.
Figure 4 shows the connections between the PROM Interface and external board logic.
The application is required to provide an external shift register with parallel-in and
parallel-out capabilities, and a parallel load register. Both devices should be
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
Table 13 Serial Port Signals
Signal Name
Pin #
Total Type
I/O
Signal Description
SICL
O14
1
LVTTL
I/O
Serial Clock line
SIDA
N14
1
LVTTL
I/O
Serial Data line
Total Pins
2
Table 14 PROM Interface Signals
Signal
Name
Pin #
Total Type
I/O
Signal Description
SPDO
N15
1
LVTTL
O
Serial Data Out
SPDI
N16
1
LVTTL
I
Serial Data In
SPLD
M16
1
LVTTL
O
When load is asserted on a positive clock
edge, the external logic performs a parallel
load. On each positive clock edge when
load is de-asserted, the shift registers shift.
When the PROM interface is idle:
if SPLD is asserted HI it indicates low
speed serial protocol,
if asserted LOW it indicates MDIO serial
protocol.
SPCK
M14
1
LVTTL
O
Clock
Total Pins
4
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