參數(shù)資料
型號： MCC501RX200TD0B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838
封裝： BGA-838
文件頁數(shù)： 46/102頁
文件大?。?/td> 1929K
代理商： MCC501RX200TD0B
January 21, 2002— Preliminary Version
C-Port Confidential
48
CHAPTER 2: SIGNAL DESCRIPTIONS
Test Signals
Test signals are described in Table 26 and their pinouts are shown in Figure 6.
During JTAG, SCLK and SCLKX must remain as differential inputs.
No Connection Pins
No connection pins are listed in Table 27.
Table 26 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
Signal Name
Pin #
Total
Type
Signal Description
JTCK
T11
1
LVTTL
Test Clock
JTMS*
Z15
1
LVTTL
Test Mode Select. High selects modes
as defined in the IEEE 1149.1 JTAG
specification.
JTRSTX
X15
1
LVTTL
Test Reset (low active)
JTDI
AB15
1
LVTTL
Test Data In
JTDO
V15
1
LVTTL
Test Data Out
JHIGHZ
T12
1
LVTTL
Turns off all output drivers when High
JCLKBYP
T13
1
LVTTL
1X or 2X Clock Mode Select. Low
selects 1X, High selects 2X.
JSE
S12
1
LVTTL
Scan Enable. High enables scan test.
JS00-JS09
L12, N13, N12, P13, P12, Q12, R13, R12,
R11, R10
10
LVTTL
Scan Out Pins
Total Pins
18
* According to the IEEE 1149.1 specification, the JTMS, JTRST, and JTDI pins must have internal pullups. While the C-5 NP does not currently have pads
with pullups, customers can pull up these three pins on the board.
Table 27 No Connection Pins
Signal Name
Pin #
Total
Type
Signal Description
NC1 - NC11
I18, H17, H18, N10, P10, N11, P11, U14,
V14, U16, V16
11
nc
Reserved for future functionality
Total Pins
11
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