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參數(shù)資料
| 型號(hào)： | MCC501RX200TD0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838 |
| 封裝： | BGA-838 |
| 文件頁(yè)數(shù)： | 30/102頁(yè) |
| 文件大?。?/td> | 1929K |
| 代理商： | MCC501RX200TD0B |
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C-Port Confidential
Preliminary Version — January 21, 2002
Pin Descriptions Grouped by Function
33
Executive Processor
System Interface Signals
The XP’s system interface manages the supervisory controls for the network interfaces, as
well as the set of pins that provide interfaces to other components in the system that are
not memories or network interfaces. It is also the primary interface used for initializing the
C-5 NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM
interface signals.
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or
66MHz. The PCI is fully compliant with PCVI Specification revision 2.1. Table 12 describes
the PCI signals.
CPn+3_2
1
LVTTL
I
RXD(4)
Receive Data
CPn+3_3
1
LVTTL
I
RXD(5)
Receive Data
CPn+3_4
1
LVTTL
I
RXD(6)
Receive Data
CPn+3_5
1
LVTTL
I
RXD(7)
Receive Data (most significant bit)
CPn+3_6
1
nc
Total Pins
28
* n can be 0, 4, 8, or 12
Reference Table 4 for pin numbers for a different cluster.
Table 11 OC-12 Signals Example (continued)
Signal Name* Pin #
Total Type
I/O
Label
Signal Description
Table 12 PCI Signals
Signal Name
Pin #
Total
Type
I/O
Signal Description
PAD0 - PAD31
T22, R21, P21, T21, R20, P20, T20,
R19, Q20, S20, R18, P19, T19,
R17, P18, T18, R16, Q18, S18, S16,
P17, T17, R15, P16, T16, S14, Q16,
T15, R14, P15, T14, Q14
32
PCI
I/O
Multiplexed Address/Data Bus. These signals are
multiplexed address and data bits. The C-5 NP
receives addresses as target and drives addresses as
master. It drives the data and receives read data as
master.
PCBEX0 - PCBEX3
N21, N20, M20, O20
4
PCI
I/O
Command byte enables. These signals are
multiplexed command and byte enabled signals.
The C-5 NP receives byte enables as target and drives
byte enables as master.
PPAR
P14
1
PCI
I/O
Parity. This signal carries even parity for AD and CBE#
pins. It has the same receive and drive characteristics
as the address and data bus, except that it is one PCI
cycle later.
PFRAMEX
K20
1
PCI
I/O
Cycle frame
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| MCC50M10 | 制造商:Thomas & Betts 功能描述:METRIC CONNECTOR 50MMSQ M10 STUD |
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| MCC50M14 | 制造商:Thomas & Betts 功能描述:METRIC CU CONNECTOR 50SQMM M14 STUD |
| MCC50M16 | 制造商:Thomas & Betts 功能描述:METRIC CU CONNECTOR 50SQMM M16 STUD |
| MCC50M6 | 制造商:Thomas & Betts 功能描述:METRIC CONNECTOR 50MMSQ M6 STUD |
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