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參數資料
| 型號： | MCC501RX200TD0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA838 |
| 封裝： | BGA-838 |
| 文件頁數： | 31/102頁 |
| 文件大小： | 1929K |
| 代理商： | MCC501RX200TD0B |
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January 21, 2002— Preliminary Version
C-Port Confidential
34
CHAPTER 2: SIGNAL DESCRIPTIONS
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following
formats:
1 An 8bit data format followed by an acknowledge bit, which supports transfers at up to
400kbps (low speed).
2 a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports
transfers up to 25MHz (high speed).
The signals and pins are identical for both the high and low speed protocols.
Which of the two data rates used is selected by the state of the PROM interface’s SPLD
signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low
speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is
selected.
The bus only supports a single master hierarchy that can operate as either a receiver or a
transmitter. The bus also supports collision detection and arbitration, and an integrated
addressing and data-transfer protocol.
Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor,
to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages
PTRDYX
L20
1
PCI
I/O
Target ready for data transfer
PIRDYX
L19
1
PCI
I/O
Initiator ready for data transfer
PSTOPX
K18
1
PCI
I/O
Target transaction stop request
PDEVSELX
N18
1
PCI
I/O
Target device selected
PPERRX
M18
1
PCI
I/O
Bus parity error
PSERRX
L18
1
PCI
I/O
System error
PCLK
L15
1
PCI
I
Bus clock
PRSTX
N17
1
PCI
I
Bus reset
PREQX
L17
1
PCI
O
Initiator bus request (arbitration)
PGNTX
N19
1
PCI
I
Initiator bus grant (arbitration)
PIDSEL
O18
1
PCI
I
Initialization device select
PINTA
O16
1
PCI
O
Interrupt
Total Pins
50
Table 12 PCI Signals (continued)
Signal Name
Pin #
Total
Type
I/O
Signal Description
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