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| 型號(hào)： | MC68HLC705KJ1CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 98/117頁(yè) |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CDW |
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MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Multifunction Timer Module
81
Data Sheet — MC68HC705KJ1
Section 9. Multifunction Timer Module
9.1 Introduction
The multifunction timer provides a timing reference with programmable real-time
interrupt capability. Figure 9-2 shows the timer organization.
9.2 Features
Features of the multifunction timer include:
Timer overflow
Four selectable interrupt rates
Computer operating properly (COP) watchdog timer
9.3 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the internal clock
signal by four, provides the timing reference for the timer functions. The value of
the first eight timer stages can be read at any time by accessing the timer counter
register at address $0009. A timer overflow function at the eighth stage allows a
timer interrupt every 1024 internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1 and RT0
bits in the timer status and control register at address $0008 allow a timer interrupt
every 16,384, 32,768, 65,536, or 131,072 clock cycles. The last four stages drive
the selectable COP system. For information on the COP, refer to Section 3.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0008
Timer Status and Control Register
(TSCR)
Read:
TOF
RTIF
TOIE
RTIE
00
RT1
RT0
Write:
TOFR
RTIFR
Reset:
00
0
0011
$0009
Timer Counter Register
(TCR)
Read:
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Write:
Reset:
00
0
0000
= Unimplemented
Figure 9-1. I/O Register Summary
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