參數(shù)資料
型號： MC68HLC705KJ1CDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 54/117頁
文件大?。?/td> 1644K
代理商： MC68HLC705KJ1CDW
Central Processor Unit (CPU)
Instruction Set
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Central Processor Unit (CPU)
41
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
4.6.1.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with
variable addresses within the first 256 memory locations. The index register
contains the low byte of the effective address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or input/output (I/O) location.
4.6.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with
variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the effective address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
4.6.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with
variable addresses at any location in memory. The CPU adds the unsigned byte in
the index register to the two unsigned bytes following the opcode. The sum is the
effective address of the operand. The first byte after the opcode is the high byte of
the 16-bit offset; the second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
4.6.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the effective branch destination by adding the signed byte following
the opcode to the contents of the program counter. If the branch condition is not
true, the CPU goes to the next instruction. The offset is a signed, two’s complement
相關(guān)PDF資料
PDF描述
MC68HC705KJ1CP 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
MC68HLC705KJ1CP 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
MC7455ARX867LG 32-BIT, 867 MHz, RISC PROCESSOR, CBGA483
MC7445ARX733LG 32-BIT, 733 MHz, RISC PROCESSOR, CBGA360
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