參數(shù)資料
型號(hào)： MC68HLC705KJ1CDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 76/117頁
文件大小： 1644K
代理商： MC68HLC705KJ1CDW
Low-Power Modes
Effects of Stop and Wait Modes
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Low-Power Modes
61
6.3.2 CPU
Effects of STOP and WAIT on the CPU are discussed here.
6.3.2.1 STOP
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling
external interrupts
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
6.3.2.2 WAIT
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling
interrupts
Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
6.3.3 COP Watchdog
Effects of STOP and WAIT on the COP watchdog are discussed here.
6.3.3.1 STOP
The STOP instruction:
Clears the COP watchdog counter
Disables the COP watchdog clock
NOTE:
To prevent the STOP instruction from disabling the COP watchdog, program the
stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog counter
immediately begins counting from $0000 and continues counting throughout the
oscillator stabilization delay.
NOTE:
Immediately after exiting stop mode by external interrupt, service the COP to
ensure a full COP timeout period.
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