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參數(shù)資料
| 型號： | MC68HLC705KJ1CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 101/117頁 |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CDW |
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Multifunction Timer Module
Data Sheet
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
84
Multifunction Timer Module
MOTOROLA
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always reads as
logic 0. Reset clears TOFR.
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads
as logic 0. Reset clears RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits
These read/write bits select one of four real-time interrupt rates, as shown in
Table 9-1. Because the selected RTI output drives the COP watchdog,
changing the real-time interrupt rate also changes the counting rate of the COP
watchdog. Reset sets RT1 and RT0.
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent can cause a real-time
interrupt request to be missed or an additional real-time interrupt request to be
generated. To prevent this occurrence, clear the COP timer before changing RT1
and RT0.
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first eight
stages is readable at any time from the read-only timer counter register shown in
Table 9-1. Real-Time Interrupt Rate Selection
RT1:RT0
RTI Rate
RTI Period
(fOP = 2 MHz)
COP Timeout Period
(–0/+1 RTI Period)
Minimum COP Timeout
Period
(fOP = 2 MHz)
00
fOP ÷ 2
14
8.2 ms
8 x RTI Period
65.5 ms
01
fOP ÷ 2
15
16.4 ms
8 x RTI Period
131.1 ms
10
fOP ÷ 2
16
32.8 ms
8 x RTI Period
262.1 ms
11
fOP ÷ 2
17
65.5 ms
8 x RTI Period
524.3 ms
Address:
$0009
Bit 7
654321
Bit 0
Read:
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
Write:
Reset:
00000000
= Unimplemented
Figure 9-4. Timer Counter Register (TCR)
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