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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 70/117頁(yè) |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CDW |
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External Interrupt Module (IRQ)
Data Sheet
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
56
External Interrupt Module (IRQ)
MOTOROLA
5.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected to the IRQ
pin input of the CPU if enabled by the PIRQ bit in the mask option register. This
capability allows keyboard scan applications where the transitions or levels on the
I/O pins will behave the same as the IRQ/VPP pin except for the inverted phase
(logic 1, rising edge). The active state of the IRQ/VPP pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a group to function as IRQ interrupts and are
enabled by the IRQE bit in the IRQ status and control register. The PA0–PA3 pins
can be positive-edge triggered only or positive-edge and high-level triggered.
If edge- and level-sensitive triggering is selected, a rising edge or a high level on a
PA0–PA3 pin latches an external interrupt request. Edge- and level-sensitive
triggering allows the use of multiple wired-OR external interrupt sources. As long
as any source is holding a PA0–PA3 pin high, an external interrupt request is
latched, and the CPU continues to execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3 pin
latches an external interrupt request. A subsequent external interrupt request can
be latched only after the voltage level of the previous interrupt signal returns to logic
0 and then rises again to logic 1.
NOTE:
The BIH and BIL instructions apply only to the level on the IRQ/VPP pin itself and
not to the output of the logic OR function with the PA0–PA3 pins. The state of the
individual port A pins can be checked by reading the appropriate port A pins as
inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether these pins
are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external interrupts
(PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables all maskable
interrupt requests, including external interrupt requests.
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