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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1CDW |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 108/117頁(yè) |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CDW |
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Electrical Specifications
Data Sheet
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
90
Electrical Specifications
MOTOROLA
10.6 3.3-V DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
(ILoad = –0.8 mA) PA4–PA7
(ILoad = –1.5 mA) PA0–PA3, PB2–PB3
VOH
VDD –0.3
—
V
Output low voltage
(ILoad = 5.0 mA) PA4–PA7
(ILoad = 3.5 mA) PA0–PA3, PB2–PB3
VOL
—
0.5
V
Input high voltage
PA0–PA7, PB2–PB3, IRQ/VPP, RESET, OSC1
VIH
0.7
× V
DD
—
VDD
V
Input low voltage
PA0–PA7, PB2–PB3, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2
× V
DD
V
Supply current (fOP = 1.0 MHz; fOSC = 2.0 MHz)
Run mode(3)
Wait mode(4)
Stop mode(5)
IDD
—
1.2
0.3
0.1
2.5
0.8
5.0
mA
A
Supply current (fOP = 2.1 MHz; fOSC = 4.2 MHz)
Run mode(3)
Wait mode(4)
Stop mode(5)
IDD
—
1.4
0.3
0.1
3.0
1.0
5.0
mA
A
I/O ports hi-z leakage current
PA0–PA7, PB2–PB3 (without individual pulldown activated)
IIL
—0.1
±1
A
Input pulldown current
PA0–PA7, PB2–PB3 (with individual pulldown activated)
IIL
12
30
100
A
Input pullup current
RESET
IIL
–10
–25
–45
A
Input current(6)
RESET, IRQ/VPP, OSC1
IIn
—0.1
±1
A
Capacitance
Ports (as inputs or outputs)
RESET, IRQ/VPP, OSC1, OSC2
COut
CIn
—
12
8
pF
Crystal/ceramic resonator oscillator mode internal resistor
OSC1 to OSC2(7)
ROSC
1.0
2.0
3.0
M
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. Typical values at midpoint of voltage range, 25
°C only
3. Run mode IDD is measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF
on all outputs; CL = 20 pF on OSC2.
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave
clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V;
VIH = VDD – 0.2 V.
6. Only input high current rated to +1
A on RESET.
7. The ROSC value selected for RC oscillator versions of this device is unspecified.
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