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參數資料
| 型號： | MC68HLC705KJ1CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 84/117頁 |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CDW |
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Parallel I/O Ports (PORTS)
Port B
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Parallel I/O Ports (PORTS)
69
7.3 Port B
Port B is a 2-bit bidirectional port.
7.3.1 Port B Data Register
The port B data register contains a latch for each port B pin.
PB[3:2] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin
is under the control of the corresponding bit in data direction register B. Reset has
no effect on port B data.
NOTE:
PB4–PB5 and PB0–PB1 should be configured as inputs at all times. These bits are
available for read/write but are not available externally. Configuring them as inputs
will ensure that the pulldown devices are enabled, thus properly terminating them.
7.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an
output.
Address:
$0001
Bit 7
654321
Bit 0
Read:
0
See Note
PB3
PB2
See Note
Write:
Reset:
Unaffected by reset
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are
available for read/write but are not available externally. Configuring them as inputs will
ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-6. Port B Data Register (PORTB)
Address:
$0005
Bit 7
654321
Bit 0
Read:
0
See Notes
DDRB3
DDRB2
See Note
Write:
Reset:
00000000
= Unimplemented
Note:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These
bits are available for read/write but are not available externally. Configuring them as inputs
will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-7. Data Direction Register B (DDRB)
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