參數(shù)資料
型號(hào)： MC68HLC705KJ1CDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 90/117頁
文件大?。?/td> 1644K
代理商： MC68HLC705KJ1CDW
Resets and Interrupts
Data Sheet
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
74
Resets and Interrupts
MOTOROLA
A 4064-tcyc (internal clock cycle) delay after the oscillator becomes active allows
the clock generator to stabilize. If any reset source is active at the end of this delay,
the MCU remains in the reset condition until all reset sources are inactive.
Figure 8-2. Power-On Reset Timing
8.2.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 tcyc generates an external reset. A
Schmitt trigger senses the logic level at the RESET pin.
Figure 8-3. External Reset Timing
OSCILLATOR STABILIZATION DELAY(2)
VDD
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
INTERNAL
DATA BUS
1. Power-on reset threshold is typically between 1 V and 2 V.
2. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
$07FE
$07FF
NEW PCH
NEW PCL
(NOTE 1)
3. Internal clock, internal address bus, and internal data bus are not available externally.
Table 8-1. External Reset Timing
Characteristic
Symbol
Min
Max
Unit
RESET Pulse Width
tRL
1.5
—
tcyc
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
INTERNAL
DATA BUS
$07FE
$07FF
NEW PC
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
NEW
PCH
tRL
NEW PC
NEW
PCL
DUMMY
OP
CODE
RESET
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