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參數(shù)資料
| 型號： | MC68HLC705KJ1CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 93/117頁 |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CDW |
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Resets and Interrupts
Interrupts
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Resets and Interrupts
77
8.3.3 Timer Interrupts
The timer can generate the following interrupt requests:
Real time
Timer overflow
Setting the I bit in the condition code register disables timer interrupts.
8.3.3.1 Real-Time Interrupt
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while
the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer
status and control register.
8.3.3.2 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF, becomes
set while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE
are in the timer status and control register.
8.3.4 Interrupt Processing
The CPU takes the following actions to begin servicing an interrupt:
Stores the CPU registers on the stack in the order shown in
Sets the I bit in the condition code register to prevent further interrupts
Table 8-2. External Interrupt Timing (VDD = 5.0 Vdc)
(1)
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note(2)
2. The minimum tILIL should not be less than the number of interrupt service routine cycles plus
19 tcyc.
—
tcyc
Table 8-3. External Interrupt Timing (VDD = 3.3 Vdc)
(1)
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note(2)
2. The minimum tILIL should not be less than the number of interrupt service routine cycles plus
19 tcyc.
—
tcyc
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