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參數(shù)資料
| 型號： | MC68HLC705KJ1CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 51/117頁 |
| 文件大?。?/td> | 1644K |
| 代理商： | MC68HLC705KJ1CDW |
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Central Processor Unit (CPU)
CPU Registers
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Central Processor Unit (CPU)
39
4.5.5 Condition Code Register
The condition code register is an 8-bit register whose three most significant bits are
permanently fixed at 111. The condition code register contains the interrupt mask
and four flags that indicate the results of the instruction just executed.
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of
the accumulator during an ADD or ADC operation. The half-carry flag is required
for binary-coded decimal (BCD) arithmetic operations.
I — Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request occurs
while the interrupt mask is logic 0, the CPU saves the CPU registers on the
stack, sets the interrupt mask, and then fetches the interrupt vector. If an
interrupt request occurs while the interrupt mask is logic 1, the interrupt request
is latched. Normally, the CPU processes the latched interrupt request as soon
as the interrupt mask is cleared again.
A return from interrupt instruction (RTI) unstacks the CPU registers, restoring
the interrupt mask to its cleared state. After any reset, the interrupt mask is set
and can be cleared only by a software instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a negative
result.
Z — Zero Flag
The CPU sets the zero flag when an ALU operation produces a result of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a
carry out of bit 7 of the accumulator or when a subtraction operation requires a
borrow. Some logical operations and data manipulation instructions also clear
or set the carry/borrow flag.
Bit 7
654321
Bit 0
Read:
1
HIN
Z
C
Write:
Reset:
111
U
1
U
= Unimplemented
U = Unaffected
Figure 4-6. Condition Code Register (CCR)
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