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參數(shù)資料
| 型號(hào)： | MC68HC08LT8CFGE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44 |
| 文件頁(yè)數(shù)： | 93/156頁(yè) |
| 文件大?。?/td> | 1107K |
| 代理商： | MC68HC08LT8CFGE |
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SIM Counter
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
41
4.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the
LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively
pulls down the RST pin for all internal reset sources.
4.3.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is
entered in the condition where the reset vectors are blank ($FF). (See Chapter 15 Development Support.)
When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all
internal reset sources.
4.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of
CGMXCLK.
4.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator module (OSC) to drive
the bus clock state machine.
4.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a logic 1, then the stop recovery is reduced from
the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC cleared.
4.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 4.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 4.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
4.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
Interrupts:
–
Maskable hardware CPU interrupts
–
Non-maskable software interrupt instruction (SWI)
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| MC68HC08MR4 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:In-Circuit Simulator |
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