參數(shù)資料
型號： MC68HC08LT8CFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù)： 111/156頁
文件大?。?/td> 1107K
代理商： MC68HC08LT8CFGE
Timer Interface Module (TIM)
MC68HC08LT8 Data Sheet, Rev. 1
58
Freescale Semiconductor
6.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
6.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
6.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.
6.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 6.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
$002F
TIM2 Counter Modulo
Register Low
(T2MODL)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
11111111
$0030
TIM2 Channel 0 Status
and Control Register
(T2SC0)
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
00000000
$0031
TIM2 Channel 0
Register High
(T2CH0H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0032
TIM2 Channel 0
Register Low
(T2CH0L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
$0033
TIM2 Channel 1 Status
and Control Register
(T2SC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
00000000
$0034
TIM2 Channel 1
Register High
(T2CH1H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0035
TIM2 Channel 1
Register Low
(T2CH1L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
Figure 6-2. TIM I/O Register Summary (Sheet 2 of 2)
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