參數(shù)資料
型號(hào): MC68HC08LT8CFGE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù): 17/156頁
文件大?。?/td> 1107K
代理商: MC68HC08LT8CFGE
Keyboard Interrupt Registers
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
113
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, disable the pull-up device, use the data direction
register to configure the pin as an input and then read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a logic 0 for software to
read the pin.
11.4.1 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore
a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1.
Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2.
Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
3.
Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4.
Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1.
Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction
register A.
2.
Write logic 1’s to the appropriate port A data register bits.
3.
Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
11.5 Keyboard Interrupt Registers
Two registers control the operation of the keyboard interrupt module:
Keyboard status and control register
Keyboard interrupt enable register
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