參數(shù)資料
型號： MC68HC08LT8CFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù)： 83/156頁
文件大?。?/td> 1107K
代理商： MC68HC08LT8CFGE
Configuration Register (CONFIG)
MC68HC08LT8 Data Sheet, Rev. 1
32
Freescale Semiconductor
3.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001D and $001F. The configuration
registers may be read at anytime.
NOTE
The options except LVIT[1:0] and LVIPWRD are one-time writable by the
user after each reset. The LVIT[1:0] and LVIPWRD bits are one-time
writable by the user only after each POR (power-on reset). The CONFIG
registers are not in the FLASH memory but are special registers containing
one-time writable latches after each reset. Upon a reset, the CONFIG
registers default to predetermined settings as shown in Figure 3-2 and
The mask option register (MOR) is used to select the oscillator option for the MCU: crystal oscillator or
RC oscillator. The MOR is implemented as a byte in FLASH memory. Hence, writing to the MOR requires
programming the byte.
3.3 Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS.
1 = COP timeout period is (213 – 24) CGMXCLK cycles
0 = COP timeout period is (218 – 24) CGMXCLK cycles
LVISTOP — Low Voltage Inhibit Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — Low Voltage Inhibit Reset Disable
LVIRSTD disables the reset signal from the LVI module. Reset clears LVIRSTOP.
1 = LVI module reset disabled
0 = LVI module reset enabled
Address: $001F
Bit 7
654321
Bit 0
Read:
COPRS
LVISTOP
LVIRSTD
LVIPWRD
R
SSREC
STOP
COPD
Write:
Reset:
000
U
0000
POR:
00000000
R
= Reserved
U = Unaffected
Figure 3-2. Configuration Register 1 (CONFIG1)
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