參數(shù)資料
型號： MC68HC08LT8CFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù)： 54/156頁
文件大?。?/td> 1107K
代理商： MC68HC08LT8CFGE
2-V DC Electrical Characteristics
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
147
16.7 2-V DC Electrical Characteristics
Table 16-6. DC Electrical Characteristics (2V)
Characteristic(1)
1. VDD = 1.8 to 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
Symbol
Min
Typ(2)
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C only.
Max
Unit
Output high voltage (ILOAD = –0.4 mA)
All ports
VOH
VDD–0.5
——
V
Output low voltage
(ILOAD = 0.5mA) All ports except PTB2–PTB3
(ILOAD = 8mA) PTB2–PTB3
VOL
——
0.5
V
Input high voltage
All ports, RST, IRQ, OSC1
VIH
0.7
× V
DD
—
VDD
V
Input low voltage
All ports, RST, IRQ, OSC1
VIL
VSS
—
0.3
× V
DD
V
VDD supply current, fOP = 1MHz (RLCD = 146k)
Run(3)
with all modules on
Wait(4)
with all modules off, except PPI, LCD, and LVI
Stop(5)
–40 to 85
°C (All modules off)
25
°C (XTAL, LCD, PPI enabled)
25
°C (XTAL, LCD, PPI, LVI enabled)
25
°C (XTAL, LCD, PPI, LVI, OSC enabled)
3. Run (operating) IDD measured using external square wave clock source (fOP = 1 MHz). All inputs 0.2V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 1 MHz). All inputs 0.2V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current.
IDD
—
0.8
0.6
0.2
5
147
0.5
2
1.8
1
15
155
1
mA
A
mA
Digital I/O ports Hi-Z leakage current
IIL
——
± 10
A
Input current
IIN
——
± 1
A
Capacitance
Ports (as input or output)
COUT
CIN
—
12
8
pF
POR rearm voltage(6)
6. Maximum is highest voltage that POR is guaranteed.
VPOR
750
—
mV
POR rise time ramp rate(7)
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
RPOR
0.02
—
V/ms
Monitor mode entry voltage
VTST
VDD + 2.5
—9.1
V
Pullup resistors(8)
PTA0–PTA3 as KBI0–KBI3, RST, IRQ
8. RPU is measured at VDD = 5.0V.
RPU
50
100
200
k
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