參數(shù)資料
型號: MC68HC08LT8CFGE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù): 156/156頁
文件大小: 1107K
代理商: MC68HC08LT8CFGE
Port B
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
99
9.3.2 Data Direction Register B (DDRB)
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to
a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
NOTE
For devices packaged in a 44-pin package, PTB6–PTB7 are not connected.
DDRB6:7 should be set to a 1 to configure PTB6–PTB7 as outputs.
DDRB[7:6, 3:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:6, 3:0], configuring all port B
pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 9-7 shows the port
B I/O logic.
Figure 9-7. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 9-3 summarizes the operation of the port B pins.
Address:
$0005
Bit 7
6
54
32
1
Bit 0
Read:
DDRB7
DDRB6
00
DDRB3
DDRB2
DDRB1
DDRB0
Write:
Reset:
000
00
000
Figure 9-6. Data Direction Register B (DDRB)
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
READ PTB ($0001)
PTBX
DDRBX
PTBX
INTERNA
LD
AT
A
B
U
S
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